Patents
Patents for G11C 7 - Arrangements for writing information into, or reading information out from, a digital store (53,197)
08/2005
08/16/2005US6930954 Non-volatile semiconductor memory device
08/16/2005US6930953 Self-timed strobe generator and method for use with multi-strobe random access memories to increase memory bandwidth
08/16/2005US6930952 Method of reading memory device in page mode and row decoder control circuit using the same
08/16/2005US6930951 Semiconductor memory device capable of accessing data in continuous burst mode regardless of location of accessed data
08/16/2005US6930950 Semiconductor memory device having self-precharge function
08/16/2005US6930945 Semiconductor memory device and control method thereof
08/16/2005US6930942 Method and apparatus for measuring current as in sensing a memory cell
08/16/2005US6930941 Semiconductor memory device having potential amplitude of global bit line pair restricted to partial swing
08/16/2005US6930940 Semiconductor memory device with read and/or write column select gate
08/16/2005US6930939 Semiconductor memory device having hierarchical structure of data input/output line and precharge method thereof
08/16/2005US6930935 Redundancy circuit and semiconductor device using the same
08/16/2005US6930934 High efficiency redundancy architecture in SRAM compiler
08/16/2005US6930932 Data signal reception latch control using clock aligned relative to strobe signal
08/16/2005US6930929 Simultaneous read-write memory cell at the bit level for a graphics display
08/16/2005US6930922 Reading circuit, reference circuit, and semiconductor memory device
08/16/2005US6930920 Low voltage non-volatile memory cell
08/16/2005US6930907 FeRAM semiconductor memory
08/16/2005US6930902 Device for storing information and a method for partial write and restore
08/16/2005US6930525 Methods and apparatus for delay circuit
08/16/2005US6930516 Comparator circuits having non-complementary input structures
08/16/2005US6930513 Simultaneous bi-directional signal transmission system and semiconductor device therefor
08/16/2005US6930370 Memory with conductors between or in communication with storage units
08/11/2005WO2005073982A1 Integrated circuit device with a rom matrix
08/11/2005WO2005073974A1 Memory device having multiple-function strobe terminals
08/11/2005WO2004109752A3 Signal integrity checking circuit
08/11/2005US20050176462 Systems and methods for reducing power consumption in a receiver
08/11/2005US20050175318 Editting apparatus and editting method
08/11/2005US20050174878 Semiconductor memory module, memory system, circuit, semiconductor device, and DIMM
08/11/2005US20050174871 Integrated circuit devices having reducing variable retention characteristics
08/11/2005US20050174870 SRAM device
08/11/2005US20050174869 System and method for data storage and tracking
08/11/2005US20050174867 Semiconductor memory device and connecting method of sense amplifier
08/11/2005US20050174866 Semiconductor integrated circuit device
08/11/2005US20050174865 Driver circuit for display device and display device
08/11/2005US20050174864 Voltage regulating circuit and method of regulating voltage
08/11/2005US20050174863 Integrated semiconductor memory having redundant memory cells
08/11/2005US20050174860 Apparatus and method for controlling enable time of signal controlling operation of data buses of memory device
08/11/2005US20050174859 Bias voltage applying circuit and semiconductor memory device
08/11/2005US20050174858 Semiconductor memory device and data read and write method of the same
08/11/2005US20050174847 Nrom flash memory cell with integrated dram
08/11/2005US20050174827 [device and method for compensating defect in semiconductor memory]
08/11/2005US20050174164 Integrated semiconductor memory with temperature-dependent voltage generation
08/11/2005US20050174144 Look-up table
08/11/2005US20050173750 Semiconductor device with improved overlay margin and method of manufacturing the same
08/11/2005US20050172787 Music reproducing system
08/11/2005DE19925881B4 Integrierter Speicher mit in Kreuzungspunkten von Wortleitungen und Bitleitungen angeordneten Speicherzellen Integrated memory having arranged at crossover points of word lines and bit lines of memory cells
08/11/2005DE102004062194A1 Integrierte Halbleiterschaltungs-Vorrichtung A semiconductor integrated circuit device
08/11/2005DE102004022792A1 Memory circuit for data storage esp. for mobile/cell phone, has control circuit for blocking and enabling read/write functions in first and second state
08/11/2005DE102004013929B3 Control method for the reading in of a data signal to an electronic circuit input latch, especially to a DRAM circuit, whereby the delay between signal and clock flanks is set so that it is within a defined time window
08/11/2005DE102004006769B3 Auslesevorrichtung Readout device
08/10/2005EP1562201A2 Bias voltage applying circuit and semiconductor memory device
08/10/2005EP1561587A1 Inkjet printer identification circuit
08/10/2005CN1653552A Serially sensing the output of multilevel cell arrays
08/10/2005CN1652252A Semiconductor device
08/10/2005CN1652251A Method for implementing table looking-up controller in dynamic memory
08/10/2005CN1652250A Redundancy relieving circuit
08/10/2005CN1652248A Method and memory system in which operating mode is set using address signal
08/10/2005CN1652096A Apparatus and method for use of memory devices for audio
08/10/2005CN1652086A Memory controller capable of estimating memory power consumption
08/10/2005CN1651246A Identification circuit of ink jet printing head and its method
08/10/2005CN1214396C Semiconductor storage having data masking pin and storage system including the same
08/10/2005CN1214395C Memory address generator circuit and semiconductor memory device
08/10/2005CN1214394C Electric circuit device for storing unit data content value computation
08/10/2005CN1214393C Data determining circuitry and data determining method
08/09/2005US6928594 Semiconductor integrated circuit
08/09/2005US6928575 Apparatus for controlling and supplying in phase clock signals to components of an integrated circuit with a multiprocessor architecture
08/09/2005US6928527 Look ahead methods and apparatus
08/09/2005US6928494 Method and apparatus for timing-dependant transfers using FIFOs
08/09/2005US6928028 Synchronous dynamic random access memory for burst read/write operations
08/09/2005US6928027 Virtual dual-port synchronous RAM architecture
08/09/2005US6928026 Synchronous global controller for enhanced pipelining
08/09/2005US6928025 Synchronous integrated memory
08/09/2005US6928024 RAM memory circuit and method for memory operation at a multiplied data rate
08/09/2005US6928023 Apparatus for and method of controlling AIVC through block selection information in semiconductor memory device
08/09/2005US6928020 Semiconductor memory device
08/09/2005US6928019 Semiconductor device with self refresh test mode
08/09/2005US6928017 Semiconductor memory device
08/09/2005US6928014 Semiconductor memory device reducing noise
08/09/2005US6928013 Timing control method for operating synchronous memory
08/09/2005US6928012 Bitline equalization system for a DRAM integrated circuit
08/09/2005US6928009 Redundancy circuit for memory array and method for disabling non-redundant wordlines and for enabling redundant wordlines
08/09/2005US6928008 Semiconductor memory devices with data line redundancy schemes and method therefore
08/09/2005US6928007 ODT mode conversion circuit and method
08/09/2005US6928006 Semiconductor memory device capable of reducing noise during operation thereof
08/09/2005US6928005 Domino comparator capable for use in a memory array
08/09/2005US6928004 Semiconductor memory device
08/09/2005US6928000 Semiconductor memory device having a resistance adjustment unit
08/09/2005US6927996 Magnetic memory device
08/09/2005US6927992 Trace-impedance matching at junctions of multi-load signal traces to eliminate termination
08/09/2005US6927430 Shared bit line cross-point memory array incorporating P/N junctions
08/04/2005WO2005071555A1 Apparatus and method for use of memory devices for audio
08/04/2005WO2005036557A3 Ac sensing for a resistive memory
08/04/2005US20050172095 Dual edge command in DRAM
08/04/2005US20050171765 Recording apparatus, reproducing apparatus, and recording and/or reproducing apparatus
08/04/2005US20050171764 Recording apparatus, reproducing apparatus, and recording and/or reproducing apparatus
08/04/2005US20050169095 Bit line discharge control method and circuit for a semiconductor memory
08/04/2005US20050169092 Network packet buffer allocation optimization in memory bank systems
08/04/2005US20050169090 Method for making high performance semiconductor memory devices
08/04/2005US20050169087 Semiconductor memory device capable of operating at high speed and with low power consumption while ensuring reliability of memory cell
08/04/2005US20050169084 Semiconductor memory device and method of refreshing the semiconductor memory device