Patents
Sitemap › G11 - Information storage › G11C - Static stores › G11C 7 - Arrangements for writing information into, or reading information out from, a digital store
Patents for G11C 7 - Arrangements for writing information into, or reading information out from, a digital store (53,197)
08/2005
08/25/2005CA2553130A1 Secured phase-change devices
08/24/2005EP1566809A1 Sensing circuit with regulated reference voltage
08/24/2005EP1181691B1 Read-write amplifier for a dram memory cell and dram memory
08/24/2005CN2720573Y Device for detecting and correcting error in refresh time-pulse of dynamic random access internal storage
08/24/2005CN2720571Y Voice recording playing device
08/24/2005CN2720570Y Clip-type voice recording-playing device
08/24/2005CN1659663A Semiconductor memory device with test mode to monitor internal timing control signals at I/O terminals
08/24/2005CN1659659A Roll back method for a smart card
08/24/2005CN1659658A Single-ended current sense amplifier
08/24/2005CN1658325A Memory device with different termination units for different signal frequencies
08/24/2005CN1658169A Memory control method and correlation device
08/24/2005CN1657930A Device for investigating quality of wine
08/23/2005US6934903 Using microcode to correct ECC errors in a processor
08/23/2005US6934816 Integrated circuit memory devices having asynchronous flow-through capability
08/23/2005US6934465 Audio and/or video data recording and reproducing apparatus and method of same
08/23/2005US6934216 Semiconductor memory device
08/23/2005US6934215 Semiconductor memory device having duty cycle correction circuit and interpolation circuit interpolating clock signal in the semiconductor memory device
08/23/2005US6934214 Semiconductor memory device having a hierarchical I/O structure
08/23/2005US6934213 Method and apparatus for reducing write power consumption in random access memories
08/23/2005US6934209 Temperature compensated T-RAM memory device and method
08/23/2005US6934208 Apparatus and method for a current limiting bleeder device shared by columns of different memory arrays
08/23/2005US6934207 Flash array implementation with local and global bit lines
08/23/2005US6934204 Semiconductor device with reduced terminal input capacitance
08/23/2005US6934201 Asynchronous, high-bandwidth memory component using calibrated timing elements
08/23/2005US6934200 Yield and speed enhancement of semiconductor integrated circuits using post fabrication transistor mismatch compensation circuitry
08/23/2005US6934199 Memory device and method having low-power, high write latency mode and high-power, low write latency mode and/or independently selectable write latency
08/23/2005US6934198 First-in, first-out buffer system in an integrated circuit
08/23/2005US6934197 Method and circuit configuration for digitizing a signal in an input buffer of a DRAM device
08/23/2005US6934183 Method and apparatus for resetable memory and design approach for same
08/23/2005US6934181 Reducing sub-threshold leakage in a memory array
08/23/2005US6934176 Systems for programmable memory using silicided poly-silicon fuses
08/23/2005US6934174 Reconfigurable memory arrays
08/23/2005US6933755 Output driving circuit for maintaining I/O signal duty ratios
08/23/2005CA2294027C Method and apparatus for audibly indicating when a predetermined location has been encountered in stored data
08/18/2005WO2005006822A3 Battery pack with built-in communication port
08/18/2005US20050182997 Semiconductor device with memory and method for memory test
08/18/2005US20050182961 Electronic data processing device
08/18/2005US20050182914 Synchronous dram system with control data
08/18/2005US20050182868 Apparatus and method for controlling memory
08/18/2005US20050181554 Semiconductor memory device and method for initializing the same
08/18/2005US20050181546 Methods for fabricating fuse programmable three dimensional integrated circuits
08/18/2005US20050180729 Editing apparatus and editing method
08/18/2005US20050180255 Memory device having a read pipeline and a delay locked loop
08/18/2005US20050180254 Method of performing access to a single-port memory device, memory access device, integrated circuit device and method of use of an integrated circuit device
08/18/2005US20050180249 Memory array and method with simultaneous read/write capability
08/18/2005US20050180246 High speed DRAM architecture with uniform access latency
08/18/2005US20050180243 Semiconductor device
08/18/2005US20050180242 Semiconductor storage device
08/18/2005US20050180240 Method and system for fast memory access
08/18/2005US20050180239 Method and system for providing temperature dependent programming for magnetic memories
08/18/2005US20050180236 Precharge circuit for DC/DC boost converter startup
08/18/2005US20050180235 Memory device with different termination units for different signal frequencies
08/18/2005US20050180233 Software power control of circuit modules in a shared and distributed DMA system
08/18/2005US20050180231 Complimentary lateral nitride transistors
08/18/2005US20050180230 Method and structure for enabling a redundancy allocation during a multi-bank operation
08/18/2005US20050180229 On die termination mode transfer circuit in semiconductor memory device and its method
08/18/2005US20050180228 Method and circuit for dynamic read margin control of a memory array
08/18/2005US20050180224 Differential current-mode sensing methods and apparatuses for memories
08/18/2005US20050180221 Data storage unit, data storage controlling apparatus and method, and data storage controlling program
08/18/2005US20050180208 Skewed sense AMP for variable resistance memory sensing
08/18/2005US20050180205 Magnetic random access memory and method of reading data from the same
08/18/2005US20050180200 Bit line control for low power in standby
08/18/2005US20050180195 Memory device using nano tube cell
08/18/2005US20050180188 Phase-change memory device with overvoltage protection and method for protecting a phase-change memory device against overvoltages
08/18/2005US20050179492 Memory component with improved noise insensitivity
08/18/2005US20050179478 Device to be used in the synchronization of clock pulses, as well as a clock pulse synchronization process
08/18/2005DE102004039236A1 Magnetic RAM cell read operation performing method for use in data storage device, involves determining whether voltage change is occurred at node between two RAM cells based on applying write sense current across one cell
08/18/2005DE102004039235A1 Read operation performing method for use in memory cell string, involves applying write sense current across magnetic random access memory cell, and determining whether one voltage across string differs from another voltage
08/18/2005DE102004004026A1 Circuitry for data storage, especially dynamic random access memory (DRAM) with flexibly arranged circuit chips for memory cell units and data transmission units, without faults in units causing total breakdown of entire circuitry
08/17/2005EP1564950A1 Timing signal generator
08/17/2005EP1564949A1 Reduction of common mode signals
08/17/2005EP1564948A1 Digital transmission with controlled rise and fall times
08/17/2005EP1564751A1 Information storage device, information storage method, and information storage program
08/17/2005EP1564750A2 Magnetic random access memory and method of reading data from the same
08/17/2005EP1564749A2 Multi-port memory based on DRAM core
08/17/2005EP1564748A2 Multi-port memory based on DRAM core
08/17/2005EP1563507A1 Cascode amplifier circuit for producing a fast, stable and accurate bit line voltage
08/17/2005EP1563494A1 Recording medium, method of configuring control information thereof, recording and/or reproducing method using the same, and apparatus thereof
08/17/2005CN2718733Y Moving storage magnetic disk with alarm
08/17/2005CN1656460A Pseudo multiport data memory having stall facility
08/17/2005CN1655593A Camera interface and method using dma unit to flip or rotate a digital image
08/17/2005CN1655352A Method and device for storing and presetting microelectronic circuit status
08/17/2005CN1655282A Nonvolatile semiconductor memory devices
08/17/2005CN1655281A Bias voltage applying circuit and semiconductor memory device
08/17/2005CN1655280A Semiconductor storage device and refresh control method therefor
08/17/2005CN1655279A On die termination mode transfer circuit in semiconductor memory device and its method
08/17/2005CN1655277A Multifunctional data storage device and method thereof
08/17/2005CN1655223A Driver circuit for display device and display device
08/17/2005CN1655128A Architecture and method for dynamic adjustment of numerical value storage in temporary memory
08/17/2005CN1215480C Semiconductor memory device and control method therefor
08/16/2005US6931582 Memory card and memory controller
08/16/2005US6931565 Semiconductor memory
08/16/2005US6931500 Method for bus capacitance reduction
08/16/2005US6931483 Memory device having different burst order addressing for read and write operations
08/16/2005US6931482 Semiconductor memory device internally provided with logic circuit which can be readily controlled and controlling method thereof
08/16/2005US6931479 Method and apparatus for multi-functional inputs of a memory device
08/16/2005US6931474 Dual-function computing system having instant-on mode of operation
08/16/2005US6931467 Memory integrated circuit device which samples data upon detection of a strobe signal
08/16/2005US6931086 Method and apparatus for generating a phase dependent control signal
08/16/2005US6930955 Method and apparatus for establishing and maintaining desired read latency in high-speed DRAM
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