Patents
Sitemap › G11 - Information storage › G11C - Static stores › G11C 7 - Arrangements for writing information into, or reading information out from, a digital store
Patents for G11C 7 - Arrangements for writing information into, or reading information out from, a digital store (53,197)
07/2005
07/28/2005US20050162942 Semiconductor memory device performing reliable data sensing
07/28/2005US20050162941 Method and apparatus for reducing leakage current in a read only memory device using transistor bias
07/28/2005US20050162934 Status register to improve initialization of a synchronous memory
07/28/2005US20050162931 Reference current generator, and method of programming, adjusting and/or operating same
07/28/2005US20050162929 Memory system
07/28/2005US20050162903 Method of operating a stacked spin based memory
07/28/2005US20050162891 Ferroelectric memory device and method of reading a ferroelectric memory
07/28/2005US20050162185 Flip-flop circuit having majority-logic circuit
07/28/2005US20050161715 Cross point resistive memory array
07/28/2005DE10361024A1 Test process for an integrated semiconductor memory has control signals to switch between normal and test operation and testing between data read in and select transistor blocking
07/28/2005DE102004063206A1 Schaltungsanordnung und Verfahren zur ISI-Löschung Circuit arrangement and method for ISI cancellation
07/28/2005DE102004062451A1 Line layout for semiconductor memory device e.g. dynamic RAM, has conductive line arranged in the same direction as word lines in twisted area of set of twisted bit line pairs in memory device
07/28/2005DE102004061311A1 Temperaturkompensierte Verzögerungssignale Temperature compensated delay signals
07/28/2005DE102004061299A1 Eingangspuffer mit Differenzverstärker Input buffer with differential amplifier
07/28/2005DE102004040526A1 Magnetspeicherspeicherungsvorrichtung Magnetic memory storage device
07/28/2005DE102004010353A1 Einschalt-Schaltung in einer Halbleiterspeichervorrichtung A power-up circuit in the semiconductor memory device
07/28/2005DE10123514B4 Halbleiter-Speicherbaustein Semiconductor memory device
07/27/2005CN1647215A System and method for generating a reference voltage based on averaging the voltages of two complementary programmed dual bit reference cells
07/27/2005CN1647207A Storage device using resistance varying storage element and reference resistance value decision method for the device
07/27/2005CN1647204A Method of performing access to a single-port memory device, memory access device, integrated circuit device and method of use of an integrated circuit device
07/27/2005CN1647203A Methods and apparatus for adaptively adjusting a data receiver
07/27/2005CN1647049A Pipelined parallel programming operation in a non-volatile memory system
07/27/2005CN1645614A Semiconductor device
07/27/2005CN1645610A Stacked layered type semiconductor memory device
07/27/2005CN1645511A Stacked layered type semiconductor memory device
07/27/2005CN1645435A Wireless service system with location and player information correspond
07/27/2005CN1212666C Semiconductor memory
07/26/2005US6922764 Memory, processor system and method for performing write operations on a memory region
07/26/2005US6922762 Clustering storage system
07/26/2005US6922758 Synchronous flash memory with concurrent write and read operation
07/26/2005US6922750 Semiconductor memory device capable of simultaneously reading data and refreshing data
07/26/2005US6922649 Multiple on-chip test runs and repairs for memories
07/26/2005US6922372 Synchronous semiconductor memory device having stable data output timing
07/26/2005US6922370 High performance SRAM device and method of powering-down the same
07/26/2005US6922368 Apparatus and structure for rapid enablement
07/26/2005US6922367 Data strobe synchronization circuit and method for double data rate, multi-bit writes
07/26/2005US6922365 Read-out circuit for a dynamic memory circuit, memory cell array, and method for amplifying and reading data stored in a memory cell array
07/26/2005US6922358 Segmented metal bitlines
07/26/2005US6922357 Non-volatile semiconductor memory device
07/26/2005US6922354 Semiconductor memory device
07/26/2005US6922352 FeRAM having test circuit and method for testing the same
07/26/2005US6922338 Memory module with a heat dissipation means
07/26/2005US6922092 Impedance controlled output driver
07/22/2005CA2455656A1 Redundant memory architecture with defragmentation capability
07/21/2005WO2005066975A1 Flexible and area efficient column redundancy for non-volatile memories
07/21/2005WO2005066972A1 Non-volatile memory and method with block management system
07/21/2005WO2005066967A1 Method and apparatus for multiple row caches per bank
07/21/2005WO2005066966A1 Fixed phase clock and strobe signals in daisy chained chips
07/21/2005WO2005066965A2 Integral memory buffer and serial presence detect capability for fully-buffered memory modules
07/21/2005WO2005066806A1 Semiconductor storage apparatus for serial advanced technology attachment-based
07/21/2005WO2005050654A3 Back-bias voltage generator with temperature control
07/21/2005US20050160279 Apparatus and method for performing transparent output feedback mode cryptographic functions
07/21/2005US20050160245 Novel FIFO memory architecture and method for the management of the same
07/21/2005US20050160241 High performance cost optimized memory
07/21/2005US20050159830 Audio player with relay capability
07/21/2005US20050159829 Infrared audio player
07/21/2005US20050158950 Non-volatile memory cell comprising a dielectric layer and a phase change material in series
07/21/2005US20050158036 Recording medium editing apparatus based on content supply source
07/21/2005US20050158035 Recording medium editing apparatus based on content supply source
07/21/2005US20050158034 Recording medium editing apparatus based on content supply source
07/21/2005US20050158033 Recording medium editing apparatus based on content supply source
07/21/2005US20050158024 Editing apparatus and editing method
07/21/2005US20050157827 Method and circuit for writing double data rate (DDR) sampled data in a memory device
07/21/2005US20050157586 Arrangement comprising a memory device and a program-controlled unit
07/21/2005US20050157582 Semiconductor memory device with reduced power consumption for refresh operation
07/21/2005US20050157579 Memory device supporting a dynamically configurable core organization
07/21/2005US20050157576 Semiconductor memory device and refresh method for the same
07/21/2005US20050157575 Storage device and method
07/21/2005US20050157574 Semiconductor memory device and method of controlling the semiconductor memory device
07/21/2005US20050157573 Method of forming non-volatile resistance variable devices
07/21/2005US20050157571 Power transistor cell and power transistor component with fusible link
07/21/2005US20050157570 Semiconductor device
07/21/2005US20050157566 Semiconductor device with circuit for detecting abnormal waveform of signal and preventing the signal from being transmitted
07/21/2005US20050157550 Nonvolatile memory system, semiconductor memory and writing method
07/21/2005US20050157527 Semiconductor memory device
07/21/2005US20050156934 System featuring memory modules that include an integrated circuit buffer devices
07/21/2005US20050156652 Level converter
07/21/2005US20050156647 Delay signal generator circuit and memory system including the same
07/21/2005US20050156646 Method and system of calibrating the control delay time
07/21/2005US20050156627 Programmable array logic circuit employing non-volatile ferromagnetic memory cells
07/21/2005US20050156589 Semiconductor device and test method for the same
07/21/2005DE10358038A1 Integrierte Schaltung zur Speicherung von Betriebsparametern An integrated circuit for storage of operating parameters
07/21/2005DE10343524B4 Verfahren und Vorrichtung zum Betreiben von elektronischen Halbleiterbausteinen über Signalleitungen Method and device for operating electronic semiconductor components via signal lines
07/21/2005DE102004060644A1 Direktzugriffsspeicher unter Verwendung von Vorladezeitgebern in einem Testmodus Random access memory using Vorladezeitgebern in a test mode
07/21/2005DE102004060571A1 Slew rate adjusting apparatus for e.g. synchronous dynamic RAM, has slew rate control signal generation block to output slew rate control signals, and data output buffer adjusting slew rate of data signal input by control signals
07/21/2005DE102004059124A1 Prozessorbasierende Struktur und Verfahren zum Laden unausgerichteter Daten Processor-based structure and method for loading unaligned data
07/21/2005DE102004040506A1 Adressierschaltung für ein Kreuzungspunkt-Speicherarray, das Kreuzungspunkt-Widerstandselemente umfasst Addressing circuitry comprises a cross-point memory array, the cross point resistor elements
07/20/2005EP1554732A1 Highly compact non-volatile memory and method thereof
07/20/2005EP1554731A2 Cascode sense amp and column select circuit and method of operation
07/20/2005EP1121759B1 Serial-to-parallel/parallel-to-serial conversion engine
07/20/2005CN1643616A A volumetric data storage apparatus comprising a plurality of stacked matrix-addressable memory devices
07/20/2005CN1643613A Data storage circuit, data write method in the data storage circuit, and data storage device
07/20/2005CN1643611A Increasing the read signal in ferroelectric memories
07/20/2005CN1643610A Asynchronous interface circuit and method for a pseudo-static memory device
07/20/2005CN1641794A Semiconductor device
07/19/2005US6920540 Timing calibration apparatus and method for a memory device signaling system
07/19/2005US6920536 Method of accessing matrix data with address translation circuit that enables quick serial access in row or column directions
07/19/2005US6920528 Smart memory
07/19/2005US6920524 Detection circuit for mixed asynchronous and synchronous memory operation
07/19/2005US6920081 Apparatus for latency specific duty cycle correction
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