Patents
Sitemap › G11 - Information storage › G11C - Static stores › G11C 17 - Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
Patents for G11C 17 - Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards (10,133)
12/2002
12/19/2002DE10216223A1 Metal cell structure of metal programmable read only memory, has NMOS cell transistors which are shared by pair of bit cells selected by signals of word lines and virtual ground lines
12/18/2002EP1267358A1 MOS read only memory
12/18/2002EP1267356A2 ROM memory with multibit memory points
12/17/2002US6496446 Semiconductor memory device having burst readout mode and data readout method
12/17/2002US6496423 Chip ID register configuration
12/17/2002US6496405 Semiconductor memory apparatus and method for outputting data
12/12/2002WO2002099814A1 Non-volatile semiconductor storage device and production method thereof
12/12/2002US20020187620 Mask ROM and method for manufacturing the same
12/12/2002US20020186049 Command user interface with programmable decoder
12/12/2002US20020185694 Semiconductor device with address programming circuit
12/11/2002EP1265287A2 Non-volatile memory
12/11/2002EP1265286A2 Integrated circuit structure
12/11/2002EP1265253A2 Cross-Point diode memory arrays
12/11/2002EP1265248A2 Addressing a cross-point diode memory array
12/11/2002CN1096082C High-speed synchronous mask ROM with pipeline structure
12/11/2002CN1096081C Non-losable semi-conductor storage device
12/10/2002US6493414 Die information logic and protocol
12/05/2002US20020184433 High-density low-cost read-only memory circuit
12/05/2002US20020181279 Nonvolatile semiconductor memory device including correction of erratic memory cell data
12/05/2002US20020181269 Memory cell structure of metal programmable read only memory having bit cells with a shared transistor cell
12/05/2002US20020180511 Externally programmable antifuse
12/05/2002US20020179999 High speed programmable ROM, memory cell structure therefor, and method for writing data on/reading data from the programmable ROM
12/05/2002DE10126567A1 Integrated circuit used in memory circuits in silicon technology
12/04/2002CN1383156A Single chip processor with dynamic ageing testing function and dynamic ageing testing method
12/03/2002US6490219 Semiconductor integrated circuit device and method of manufacturing thereof
12/03/2002US6490218 Digital memory method and system for storing multiple bit digital data
12/03/2002US6489832 Chip information output circuit
12/03/2002US6489810 Highly reliable programmable monostable
11/2002
11/28/2002US20020176291 Method for providing a low power read only memory banking methodology with efficient bus muxing
11/28/2002US20020175349 Semiconductor Memory Device Having Auxiliary Conduction Region Of Deduced Area
11/27/2002CN1381848A 地址生成电路 Address generation circuit
11/27/2002CN1095171C Auto-program circuit in nonvolatile semiconductor memory device
11/26/2002US6487119 Non-volatile read only memory and its manufacturing method
11/26/2002US6487118 Semiconductor integrated circuit device, method of investigating cause of failure occurring in semiconductor integrated circuit device and method of verifying operation of semiconductor integrated circuit device
11/26/2002US6487117 Method for programming NAND-type flash memory device using bulk bias
11/26/2002US6486519 Semiconductor memory device with reduce coupling capacitance
11/21/2002US20020174391 Method of testing semiconductor storage device
11/21/2002US20020171448 Dc testing apparatus and semiconductor testing apparatus
11/20/2002CN1381071A Integrated circuit with programmable memory element
11/20/2002CN1094635C Zero power high speed programmable circuit device architecture
11/19/2002US6483745 Non-volatile semiconductor memory device with defect detection
11/19/2002US6483736 Vertically stacked field programmable nonvolatile memory and method of fabrication
11/19/2002US6483734 Memory device having memory cells capable of four states
11/14/2002WO2002091383A2 A secure poly fuse rom with a power-on or on-reset hardware security features and method therefor
11/14/2002WO2002091190A2 Memory with a bit line block and/or a word line block for preventing reverse engineering
11/14/2002US20020167854 Method and apparatus to conditionally precharge a partitioned read-only memory with shared wordlines for low power operation
11/14/2002US20020167831 Circuit for programming antifuse bits
11/13/2002EP1256956A2 Method and apparatus for memory
11/12/2002US6480428 Redundant circuit for memory device
11/12/2002US6480413 Two-dimensional resonant tunneling diode memory cell
11/12/2002US6479874 Semiconductor memory device having multilevel memory cell and method of manufacturing the same
11/12/2002US6479854 Capacitor/antifuse structure having a barrier-layer electrode and improved barrier layer
11/12/2002US6478231 Methods for reducing the number of interconnects to the PIRM memory module
11/07/2002WO2002078001A3 Memory device with row and column decoder circuits arranged in a checkerboard pattern under a plurality of memory arrays
11/07/2002US20020163827 Circuit for programming antifuse bits
11/07/2002US20020163034 Cell array region of a nor-type mask ROM device and fabricating method therefor
11/07/2002DE10217609A1 Ein-Chip-Mikrocomputer mit dynamischer Einbrenn-Testfunktion und dynamisches Einbrenn-Testverfahren dafür A one-chip microcomputer with a dynamic burn-in test function and dynamic burn-in test method therefor
11/06/2002EP1254398A1 Method and system for recording of information on a holographic medium
11/06/2002EP1254367A1 Structure identification methods using mass measurements
11/05/2002US6477094 Memory repair circuit using antifuse of MOS structure
11/05/2002US6477090 Semiconductor device, microcomputer and flash memory
10/2002
10/31/2002US20020161963 Single-chip microcomputer with dynamic burn-in test function and dynamic burn-in testing method therefor
10/31/2002US20020159297 Eeprom erasing method
10/31/2002DE10218272A1 Programmable memory cell for non-volatile memory (ROM) with several programmable memory cells, has virtual ground line selectively connected to ground in reaction to control signal
10/30/2002EP1252126A1 Nonredundant split/pool synthesis of combinatorial libraries
10/30/2002CN1377043A ROM circuit with mask
10/30/2002CN1377042A Programmable storage and its programming method
10/30/2002CN1093678C PMOS ROM address line decoding device
10/29/2002US6473345 Semiconductor memory device which can be simultaneously tested even when the number of semiconductor memory devices is large and semiconductor wafer on which the semiconductor memory devices are formed
10/29/2002US6473327 Semiconductor memory having a pair of bank select drivers driving each bank select line
10/29/2002US6472897 Circuit and method for trimming integrated circuits
10/29/2002US6472275 Read-only memory and method for fabricating the same
10/24/2002US20020154563 Fuse read sequence for auto refresh power reduction
10/24/2002US20020153917 Semiconductor integrated circuit and a method of testing the same
10/22/2002US6469946 Semiconductor memory and its test method
10/22/2002US6469943 Switching circuit and semiconductor device
10/22/2002US6469923 Semiconductor device with programming capacitance element
10/22/2002US6469884 Internal protection circuit and method for on chip programmable poly fuses
10/17/2002WO2002082449A1 Storing an unchanging binary code in an integrated circuit
10/16/2002EP0601068B1 Electrically erasable, directly overwritable, multibit single cell memory elements and arrays fabricated therefrom
10/16/2002CN1374661A Apparatus and method for labelling storage content
10/15/2002US6466874 A computational method system, and computer program are provided for inferring functional links from genome sequences.
10/15/2002US6466512 Method of generating address configurations for solid state memory
10/15/2002US6466503 Semiconductor memory with current distributor
10/15/2002US6466498 Discontinuity-based memory cell sensing
10/15/2002US6466487 Semiconductor device with impedance controllable output buffer
10/15/2002US6466486 Buffer circuit, and semiconductor device and semiconductor memory device including same
10/10/2002US20020145918 Architecture and scheme for a non-strobed read sequence
10/10/2002US20020145466 Internal power voltage generating circuit of semiconductor device
10/09/2002CN1373516A Memory device mfg. and assembling strcture and method
10/08/2002US6462608 Low current redundancy anti-fuse apparatus
10/08/2002US6462387 High density read only memory
10/03/2002WO2002078003A2 Method and apparatus for biasing selected and unselected array lines when writing a memory array
10/03/2002WO2002078001A2 Memory device with row and column decoder circuits arranged in a checkerboard pattern under a plurality of memory arrays
10/03/2002US20020141273 Address generating circuit
10/02/2002EP1245030A1 Memory device
10/01/2002US6459648 Fault-tolerant address logic for solid state memory
10/01/2002US6459633 Redundant encoding for buried metal fuses
10/01/2002US6459629 Memory with a bit line block and/or a word line block for preventing reverse engineering
10/01/2002US6459623 EEPROM erasing method
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