Patents
Patents for G11C 17 - Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards (10,133)
10/2003
10/15/2003EP1352395A2 Circuit arrangement for triggering a programmable connection
10/15/2003CN1449046A Memory structures
10/14/2003US6633999 Integrated circuit with on-chip data checking resources
10/14/2003US6633509 Partial selection of passive element memory cell sub-arrays for write operations
10/14/2003US6633506 Antifuse detection circuit
10/10/2003CA2424211A1 A memory device
10/09/2003WO2003083429A1 A novel highly-integrated flash memory and mask rom array architecture
10/09/2003US20030189851 Non-volatile, multi-level memory device
10/09/2003US20030189846 Double access path mask rom cell structure
10/09/2003US20030189457 Zero Static Power Programmable Fuse Cell for Integrated Circuits
10/08/2003EP1351306A2 Memory structures
10/08/2003EP1351255A2 Methods and memory structures using tunnel-junction device as control element
10/08/2003EP1351254A2 An integrated fuse with regions of different doping within the fuse neck
10/08/2003EP1351253A1 Memory structures
10/08/2003CN1123811C Signal processing system with low power consumption memory
10/07/2003US6631085 Three-dimensional memory array incorporating serial chain diode stack
10/07/2003US6630724 Gate dielectric antifuse circuits and methods for operating same
10/02/2003WO2002073624A3 Memory element, method for structuring a surface, and storage device
10/02/2003US20030186468 Tunnel-junction structures and methods
10/02/2003US20030185082 Memory chip, memory component and corresponding memory module and method
10/02/2003US20030185081 Zero Static Power Fuse for Integrated Circuits
10/02/2003US20030185080 Circuit for programming antifuse bits
10/02/2003US20030185037 Virtual ground semiconductor memory device
10/02/2003US20030185035 Complementary two transistor ROM cell
10/02/2003US20030185034 Memory structures
10/02/2003US20030183868 Memory structures
10/02/2003US20030183849 Methods and memory structures using tunnel-junction device as control element
10/01/2003CN1123009C Rom电路 Rom circuit
09/2003
09/30/2003US6628561 Small anti-fuse circuit to facilitate parallel fuse blowing
09/25/2003US20030179601 Magnetic tunneling junction antifuse device
09/25/2003US20030179598 Device for selectively providing read-only data
09/25/2003US20030179011 Integrated polysilicon fuse and diode
09/24/2003EP1346370A1 Data processing device with a memory location in which data is stored according to a wom code
09/23/2003US6625546 Structure identification methods using mass measurements
09/23/2003US6625080 Antifuse detection circuit
09/23/2003US6624485 Three-dimensional, mask-programmed read only memory
09/18/2003US20030176034 Flexible hybrid memory element
09/18/2003US20030174574 Write pulse circuit for a magnetic memory
09/18/2003US20030174568 Fuse read sequence for auto refresh power reduction
09/18/2003US20030174552 Method for rewriting data in three-dimensional optical memory device fabricated in glass by ultra-short light pulse
09/18/2003US20030174040 Apparatus and method for monitoring a state, in particular of a fuse
09/17/2003EP1344225A2 Circuit arrangement for controlling a programmable connection
09/17/2003EP1105876A4 Method and apparatus for built-in self test of integrated circuits
09/17/2003CN1442906A Flexible mixed storage element
09/16/2003US6621758 Method for providing a low power read only memory banking methodology with efficient bus muxing
09/16/2003US6621324 Redundant antifuse segments for improved programming efficiency
09/12/2003WO2003075346A2 Electrical antifuse with external capacitance used for programming
09/12/2003WO2002050838A3 Circuit arrangement for controlling a programmable connection
09/11/2003US20030172359 Circuit arrangement
09/11/2003US20030169095 Electrical antifuse with external capacitance
09/10/2003EP1343172A2 Memory system
09/10/2003EP0929899B1 Antifuse detection circuit
09/09/2003US6618311 Zero power fuse sensing circuit for redundancy applications in memories
09/09/2003US6618295 Method and apparatus for biasing selected and unselected array lines when writing a memory array
09/09/2003US6618282 High density ROM architecture with inversion of programming
09/09/2003US6617914 Electrical antifuse with external capacitance
09/09/2003US6617885 Sense amplifiers having gain control circuits therein that inhibit signal oscillations
09/09/2003US6617172 Semiconductor device having identification number, manufacturing method thereof and electronic device
09/04/2003WO2003073428A1 Multiple data state memory cell
09/04/2003WO2003052890B1 Processing a memory link with a set of at least two laser pulses
09/03/2003EP1341186A1 A flexible hybrid memory element
09/03/2003EP1340262A2 Poly fuse rom with mos device based cell structure and the method for read and write therefore
09/03/2003EP1123556A4 Fuse circuit having zero power draw for partially blown condition
09/03/2003CN1120498C Single-chip read-only memory (ROM) system
09/02/2003US6615398 Method for dividing ROM and DDFS using the same method
09/02/2003US6614697 Diode-based multiplexer
08/2003
08/28/2003WO2003071554A2 Non-volatile redundancy adresses memory
08/28/2003WO2003071553A1 Semiconductor integrated circuit
08/28/2003US20030161184 Novel highly-integrated flash memory and mask ROM array architecture
08/28/2003US20030161175 Dual memory cell
08/27/2003EP1338013A2 Circuit arrangement
08/27/2003CN1119835C Method of programming nonvolatile memory
08/27/2003CN1119814C Semiconductor stroage devie
08/26/2003US6611938 Flash memory
08/26/2003US6611457 Read-only nonvolatile memory
08/26/2003US6611165 Antifuse circuit with improved gate oxide reliabilty
08/21/2003WO2003069631A2 One-time programmable memory cell
08/21/2003WO2003069630A2 Memory cell with non-destructive one-time programming
08/21/2003WO2003069628A1 Extraction of a binary code from the physical parameters of an integrated circuit
08/21/2003WO2003069626A1 Extraction of a binary code from physical parameters of an integrated circuit
08/21/2003WO2003069550A2 Electromagnetic transponder with a programmable code
08/21/2003WO2003017427A3 Vertically-stacked, field-programmable, nonvolatile memory and method of fabrication
08/21/2003US20030156482 Single level metal memory cell using chalcogenide cladding
08/21/2003US20030156469 Fuse concept and method of operation
08/21/2003US20030156452 Multiple data state memory cell
08/21/2003US20030156442 Semiconductor memory device and multi-chip module comprising the semiconductor memory device
08/21/2003US20030155961 Redundant antifuse segments for improved programming efficiency
08/21/2003US20030155606 Method to alter chalcogenide glass for improved switching characteristics
08/20/2003CN1437767A Ultra-late programming ROM and method of manufacture
08/20/2003CN1118875C Memory unit device and producing method thereof
08/19/2003US6608498 Method for characterizing an active track and latch sense-amp (comparator) in a one time programmable (OTP) salicided poly fuse array
08/14/2003WO2003067598A2 Reading circuit for reading a memory cell
08/14/2003US20030154384 Method and arrangement for the manufacture of mask-programmed ROMs while utilizing a mask comprising a plurality of systems, as well as a corresponding computer program product and a corresponding computer-readable storage medium
08/14/2003US20030151942 Extraction of a binary code based on physical parameters of an integrated circuit
08/14/2003US20030151784 Computer-generated hologram fabrication process, and hologram-recorded medium
08/14/2003US20030151539 Extraction of a binary code based on physical parameters of an integrated circuit
08/14/2003US20030151498 Programmable-code electromagnetic transponder
08/13/2003EP0766176B1 Replacement semiconductor read-only memory
08/13/2003CN1435845A Non-Volatile semiconductor memory with charging read mode
08/13/2003CN1118069C Semiconductor memory device
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