Patents
Sitemap › G11 - Information storage › G11C - Static stores › G11C 16 - Erasable programmable read-only memories
Patents for G11C 16 - Erasable programmable read-only memories (44,373)
11/2014
11/18/2014US8891276 Memory array with local bitlines and local-to-global bitline pass gates and gain stages
11/18/2014US8891274 Semiconductor device
11/18/2014US8890233 3D memory array with improved SSL and BL contact layout
11/13/2014US20140337564 Apparatuses and methods of operating for memory endurance
11/13/2014US20140337563 Method and apparatus for configuring write performance for electrically writable memory devices
11/13/2014US20140334234 Semiconductor device including memory cell having charge accumulation layer
11/13/2014US20140334233 Method of reading memory cells with different threshold voltages without variation of word line voltage and nonvolatile memory device using the same
11/13/2014US20140334232 3d flash memory device having different dummy word lines and data storage devices including same
11/13/2014US20140334231 Nonvolatile semiconductor memory device and method for erasing data thereof
11/13/2014US20140334230 Semiconductor memory device and system having the same
11/13/2014US20140334229 Semiconductor device with floating gate and electrically floating body
11/13/2014US20140334228 Linearly related threshold voltage offsets
11/13/2014US20140332802 Semiconductor device
11/11/2014US8887011 Erased page confirmation in multilevel memory
11/11/2014US8886990 Block management schemes in hybrid SLC/MLC memory
11/11/2014US8886911 Dynamic memory cache size adjustment in a memory device
11/11/2014US8886874 System and method for low-latency addressing in flash memory
11/11/2014US8885437 Storage device and driving method thereof
11/11/2014US8885430 Semiconductor memory device and data processing system
11/11/2014US8885428 Smart read scheme for memory array sensing
11/11/2014US8885425 Semiconductor memory and method of controlling the same
11/11/2014US8885421 Semiconductor memory device
11/11/2014US8885420 Erase for non-volatile storage
11/11/2014US8885418 Adaptive double pulse BCF programming
11/11/2014US8885417 Nonvolatile semiconductor memory device
11/11/2014US8885416 Bit line current trip point modulation for reading nonvolatile storage elements
11/11/2014US8885415 Determining optimal reference voltages for progressive reads in flash memory systems
11/11/2014US8885414 Nonvolatile semiconductor memory device
11/11/2014US8885412 Erase operation with controlled select gate voltage for 3D non-volatile memory
11/11/2014US8885411 Nonvolatile semiconductor memory device
11/11/2014US8885410 Direct multi-level cell programming
11/11/2014US8885409 Non-volatile memory, method of operating the same, memory system including the same, and method of operating the system
11/11/2014US8885408 Nonvolatile semiconductor memory device for rendering the same in a busy state after inputting data therein
11/11/2014US8885407 Vertical memory cells and methods, architectures and devices for the same
11/11/2014US8885406 Memory device, memory control device, and memory control method
11/11/2014US8885405 Flash memory and associated programming method
11/11/2014US8885404 Non-volatile storage system with three layer floating gate
11/11/2014US8885383 Flash memory and layout method thereof
11/11/2014US8884283 Memory semiconductor device having aligned side surfaces
11/11/2014US8883556 Semiconductor device and manufacturing method thereof
11/11/2014US8881389 Methods of flash dual inline memory modules with flash memory
11/06/2014US20140330539 Semiconductor integrated circuit and semiconductor physical quantity sensor device
11/06/2014US20140328129 Non-volatile semiconductor storage device
11/06/2014US20140328127 Method of Managing Non-Volatile Memory and Non-Volatile Storage Device Using the Same
11/06/2014US20140328126 Flash Memory Having Dual Supply Operation
11/06/2014US20140328125 Methods of forming fine patterns in semiconductor devices
11/06/2014US20140328123 Minimal Maximum-Level Programming
11/04/2014US8880964 Block and page level bad bit line and bits screening methods for program algorithm
11/04/2014US8880954 Temperature-profiled device fingerprint generation and authentication from power-up states of static cells
11/04/2014US8880920 Systems, methods and devices for limiting current consumption by a different ramp rate upon power-up
11/04/2014US8880782 Memory array including multi-state memory devices
11/04/2014US8880781 Memory system and method of operating a memory system
11/04/2014US8880375 Test apparatus and test method
11/04/2014US8879351 Non-volatile memory bank and page buffer therefor
11/04/2014US8879347 Flash memory device and method for handling power failure thereof
11/04/2014US8879346 Mechanisms for enabling power management of embedded dynamic random access memory on a semiconductor integrated circuit package
11/04/2014US8879340 Memory device having data paths with multiple speeds
11/04/2014US8879338 Semiconductor integrated circuit and nonvolatile semiconductor storage device
11/04/2014US8879333 Soft erase operation for 3D non-volatile memory with selective inhibiting of passed bits
11/04/2014US8879332 Flash memory with read tracking clock and method thereof
11/04/2014US8879331 Shared bit line string architecture
11/04/2014US8879330 Non-volatile memory (NVM) with variable verify operations
11/04/2014US8879329 Program verify operation in a memory device
11/04/2014US8879328 Sense amplifier column redundancy
11/04/2014US8879326 Nonvolatile semiconductor memory device including plural memory cells and a dummy cell coupled to an end of a memory cell
11/04/2014US8879324 Compensation loop for read voltage adaptation
11/04/2014US8879323 Interconnection matrix using semiconductor non-volatile memory
11/04/2014US8879322 Direct multi-level cell programming
11/04/2014US8879321 Vertical non-volatile memory device and electric-electronic system having the same device
11/04/2014US8879319 Re-writing scheme for solid-state storage devices
11/04/2014US8879318 Method of storing data in nonvolatile memory device and method of operating nonvolatile memory device
11/04/2014US8879317 System and method of decoding data from memory based on sensing information and decoded data of neighboring storage elements
11/04/2014US8879316 Semiconductor device and method of generating voltages using the same
11/04/2014US8879294 Selective activation of programming schemes in analog memory cell arrays
11/04/2014US8878279 Self-aligned floating gate in a vertical memory structure
11/04/2014US8878278 Compact three dimensional vertical NAND and method of making thereof
11/04/2014US8878257 Methods and apparatus for an ISFET
11/04/2014US8878254 Semiconductor memory device
11/04/2014US8877627 Method of forming PN floating gate non-volatile storage elements and transistor having N+ gate
11/04/2014US8877591 Methods of manufacturing vertical structure nonvolatile memory devices
10/2014
10/30/2014US20140321216 Random telegraph signal noise reduction scheme for semiconductor memories
10/30/2014US20140321215 Inhibiting pillars in 3d memory devices
10/30/2014US20140321214 Programming memory cells
10/30/2014US20140321213 Biasing split gate memory cell during power-off mode
10/30/2014US20140321212 Non-volatile memory (nvm) with variable verify operations
10/30/2014US20140321211 Non-volatile memory (nvm) with variable verify operations
10/30/2014US20140321210 Method for processing data, flash memory, and terminal
10/30/2014US20140321209 Non-volatile memory device and related read method
10/30/2014US20140321208 De-duplication in flash memory module
10/30/2014US20140321207 Determining soft data for combinations of memory cells
10/30/2014US20140321206 Reading memory cell history during program operation for adaptive programming
10/30/2014US20140321205 Memory device page buffer configuration and methods
10/30/2014US20140321204 Method and apparatus for optimizing reference voltages in a nonvolatile memory
10/30/2014US20140321203 Method for performing memory access management, and associated memory device and controller thereof
10/30/2014US20140321202 Defective block management
10/28/2014USRE45222 Method of writing of writing to a flash memory including data blocks and log blocks, using a logical address having a block address portion and page identifying portion, a block address table and a page table
10/28/2014US8874992 Systems and methods to initiate updating of reference voltages
10/28/2014US8874934 Nonvolatile memory device and operating method
10/28/2014US8874834 Tracking a lifetime of write operations to a non-volatile memory storage
10/28/2014US8874832 AD HOC flash memory reference cells
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