| Patents for G06F 7 - Methods or arrangements for processing data by operating upon the order or content of the data handled (93,043) |
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| 02/27/1992 | DE4025474A1 Electronic multiplier circuit using parallel addition - has reset control block assigned to flip=flop |
| 02/27/1992 | DE4025473A1 Electronic multiplier circuit using parallel addition - has a load circulation pulse circuit instead of dual one giving lower interval for producing intermediate results |
| 02/27/1992 | DE4025468A1 Electronic division circuit using dual pulse circuit - replacing dual one to eliminate errors associated with original circuit |
| 02/27/1992 | DE4023668A1 Electronic multiplier circuit using 5211 code - changes control stage and makes only systematic changes of basic circuitry |
| 02/27/1992 | DE4018667A1 Electronic division circuit using pulse circuit - contg. two flip=flops and six and=circuits as well as AND=circuit and inverter |
| 02/26/1992 | EP0472447A1 Cellular balanced delay tree multiplier and it's method of realisation |
| 02/26/1992 | EP0472148A2 Method and apparatus for computing floating point data |
| 02/26/1992 | EP0472139A2 A floating-point processor |
| 02/26/1992 | EP0472030A2 Method and apparatus for modifying two's complement multiplier to perform unsigned magnitude multiplication |
| 02/26/1992 | EP0471927A2 System for exact arithmetic computation including quadratic extensions |
| 02/26/1992 | EP0471723A1 Digital processor for two's complement computations. |
| 02/26/1992 | CN1059042A Operational method and apparatus over gf(2m) using subfield gf(2m/2) |
| 02/25/1992 | US5091874 Encoder apparatus |
| 02/25/1992 | US5091848 Vector processor for merging vector elements in ascending order merging operation or descending order merging operation |
| 02/25/1992 | US5091660 Semiconductor logic circuit |
| 02/20/1992 | WO1992002872A1 Sin/cos generator implementation |
| 02/19/1992 | EP0471536A2 Document processing apparatus |
| 02/19/1992 | EP0471387A2 Control circuit using a read-only memory as a comparator |
| 02/18/1992 | US5090035 Linear feedback shift register |
| 02/18/1992 | US5089985 System and method for performing a sort operation in a relational database manager to pass results directly to a user without writing to disk |
| 02/12/1992 | EP0470570A2 Method and apparatus for byte order switching in a computer |
| 02/12/1992 | EP0470233A1 Apparatus for transposing digital data |
| 02/12/1992 | CN1058667A Bit storage cell in memory |
| 02/11/1992 | US5088057 Rational rate frequency generator |
| 02/11/1992 | CA1295743C High speed parallel multiplier circuit |
| 02/11/1992 | CA1295742C Method and apparatus for precise floating point exceptions |
| 02/11/1992 | CA1295706C Method and system for authentication of accreditations and of messages with zero-knowledge proof and for the signing of messages, and a station for use in such system, in particular executed as a smart card station |
| 02/05/1992 | EP0469841A1 Data round-off device |
| 02/05/1992 | EP0469761A2 Digital shift register using random access memory |
| 02/05/1992 | EP0469393A2 Arithmetic and logic units |
| 02/05/1992 | EP0469303A2 Delay equalization emulation for high speed phase modulated direct digital synthesis |
| 02/04/1992 | US5086408 Method and apparatus for merging |
| 02/04/1992 | US5086406 Circuit arrangement for decimal arithmetic |
| 02/04/1992 | US5086405 Floating point adder circuit using neural network |
| 02/03/1992 | WO1992002933A1 Bit storage cell |
| 02/03/1992 | WO1992002932A1 Associative memory |
| 02/03/1992 | WO1992002877A1 Active storage means in a reduction processor |
| 02/03/1992 | WO1992002876A1 Reduction processor |
| 02/03/1992 | WO1992002875A1 A method for performing arithmetic, logical and related operations and a numerical arithmetic unit |
| 02/03/1992 | WO1992002874A1 An arithmetic unit for structure arithmetic |
| 02/03/1992 | CA2088577A1 Active storage means in a reduction processor |
| 02/03/1992 | CA2087023A1 Bit storage cell |
| 02/03/1992 | CA2087022A1 Arithmetic unit for structure arithmetic |
| 02/03/1992 | CA2086592A1 Method performing arithmetic, logical and related operations and a numerical arithmetic unit |
| 02/03/1992 | CA2086591A1 Reduction processor |
| 02/03/1992 | CA2086539A1 Associative memory |
| 01/31/1992 | WO1992002990A1 Synchronous/asynchronous data bus with message priority handling capability and segmented memory transfer |
| 01/31/1992 | CA2022202A1 Sequential reference management for cache memories |
| 01/30/1992 | DE4022296A1 Electronic multiplier circuit without offset circuit - shifts intermediate product sums w.r.t. multiplications as required during multiple serial number addn. |
| 01/30/1992 | DE4021808A1 5211-Coded decimal iterative multiplier circuit - has negation circuit with flip=flops controlled by impulse counter |
| 01/30/1992 | DE4016522A1 Iterative multiplier circuit for 5211-coded decimal numbers - halts multiplication after processing of final multiplier digit |
| 01/29/1992 | EP0468820A2 Data processing system for single-precision and double-precision data |
| 01/29/1992 | EP0468534A2 Arithmetic logic unit |
| 01/29/1992 | EP0468530A1 Fuzzy inference device |
| 01/29/1992 | EP0468505A2 Barrel shifter |
| 01/28/1992 | US5084835 Method and apparatus for absolute value summation and subtraction |
| 01/28/1992 | US5084815 Sorting and merging of files in a multiprocessor |
| 01/23/1992 | WO1992001266A1 Device for emulating neuronal networks and process for operating it |
| 01/23/1992 | DE4123186A1 Multiplier for distributed products - has multiplicand and multiplier memories coupled by reading unit and accumulation unit |
| 01/23/1992 | DE4022252A1 Digitally controlled frequency multiplication for square wave signals - counting integer pulses in up-counter and passing result to down-counter producing corrected output pulse |
| 01/22/1992 | EP0467661A2 Signal processing and recognition |
| 01/22/1992 | EP0467640A2 A method of simulating the state of a linear feedback shift register |
| 01/22/1992 | EP0467524A2 Lookahead adder |
| 01/22/1992 | EP0466997A1 Improved digital signal processor architecture |
| 01/22/1992 | EP0466814A1 Integer divider circuit |
| 01/20/1992 | WO1992001985A1 Device and method for evaluating exponentials |
| 01/20/1992 | WO1992001984A1 Device and method for evaluating trigonometric functions |
| 01/20/1992 | WO1992001982A1 Device and method for evaluating inverse trigonometric functions |
| 01/20/1992 | WO1992001981A1 Device and method for evaluating logarithms |
| 01/20/1992 | CA2085228A1 Device and method for evaluating exponentials |
| 01/20/1992 | CA2085116A1 Device for evaluating logarithms |
| 01/20/1992 | CA2084989A1 Device for evaluating inverse trigonometric functions |
| 01/15/1992 | EP0466592A1 Device for serialisation and deserialisation of data and resulting serial digital transmission system |
| 01/15/1992 | EP0161269B1 Output compare system and method automatically controlling multiple outputs in a data processor |
| 01/15/1992 | EP0146632B1 Majority circuit |
| 01/14/1992 | US5081607 Arithmetic logic unit |
| 01/14/1992 | US5081606 Cube root calculation apparatus |
| 01/14/1992 | US5081373 Circuit and method for sampling digital data |
| 01/14/1992 | CA1294367C High speed adder |
| 01/14/1992 | CA1294366C Processor for constrained least squares computations |
| 01/09/1992 | WO1992000561A1 A generalized systolic ring serial floating point multiplier |
| 01/09/1992 | WO1992000560A1 A generalised systolic array serial floating point adder and accumulator |
| 01/08/1992 | EP0465320A2 Combined queue for invalidates and return data in multi-processsor system |
| 01/08/1992 | EP0464899A1 Multiplier circuit and system for carrying it out |
| 01/08/1992 | EP0464601A2 Arithmetic operation system |
| 01/08/1992 | EP0464493A2 High-radix divider |
| 01/08/1992 | EP0328637A4 Apparatus for computing multiplicative inverses in data encoding decoding devices |
| 01/07/1992 | US5079739 Apparatus and method for converting bit-mapped data from row orientation to column or orientation |
| 01/07/1992 | US5079736 High speed pipeline merge sorter with run length tuning mechanism |
| 01/07/1992 | US5079733 Pseudo-random sequence generator arrangement |
| 01/07/1992 | CA1294055C Apparatus and method for acceleration of effective subtraction procedures by the approximation of the absolute value of the exponent argumentdifference |
| 01/02/1992 | EP0463966A2 High-performance multi-processor having floating point unit |
| 01/02/1992 | EP0463752A2 Pattern matching circuit |
| 01/02/1992 | EP0463640A2 Memory device for simulating a shift register |
| 01/02/1992 | DE4020783A1 Fast carry propagation circuit for 5211-coded decimal arithmetic - performs addition and fast propagation of decimal carry signal with minimal gate count |
| 01/02/1992 | DE4020322A1 Multiplier circuit for 5211-coded decimal arithmetic - uses eight-decade shift register with rotation for result accumulation and additional shift registers for final result |
| 12/31/1991 | US5077677 Probabilistic inference gate |
| 12/31/1991 | US5077669 Method for quasi-key search within a national language support (nls) data processing system |
| 12/31/1991 | US5077659 Data processor employing the same microprograms for data having different bit lengths |
| 12/31/1991 | CA1293815C Dual mode adder circuitry |