Patents for G06F 13 - Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units (158,002) |
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02/02/1995 | WO1995003581A1 Method for configuring multiple adapter cards on a bus |
02/02/1995 | WO1995003571A1 Apparatus for adding modem capabilities to a computer system equipped with a digital signal processor |
02/02/1995 | DE4425726A1 Electronic device |
02/02/1995 | CA2165831A1 Method for configuring multiple adapter cards on a bus |
02/01/1995 | EP0637160A2 Distributed system for call processing |
02/01/1995 | EP0637157A2 System control method and system control apparatus |
02/01/1995 | EP0637155A1 Method and system for buffering transient data |
02/01/1995 | EP0637151A1 A method and system for maintaining processing continuity to mobile computers in a wireless network |
02/01/1995 | EP0636989A1 Multi-channel data receiver system |
02/01/1995 | EP0636985A1 Process monitoring in a multiprocessing server |
02/01/1995 | EP0636975A2 An apparatus for and a method of controlling cooperative operations |
02/01/1995 | EP0636973A2 Processor interface chip for dual-microprocessor processor system |
02/01/1995 | EP0636260A1 Externally updatable rom (eurom) |
02/01/1995 | EP0636259A1 Cryptographic data security in a secured computer system. |
02/01/1995 | CN1098207A Integrated control system for distributed processing |
01/31/1995 | US5386579 Minimum pin-count multiplexed address/data bus with byte enable and burst address counter support microprocessor transmitting byte enable signals on multiplexed address/data bus having burst address counter for supporting signal datum and burst transfer |
01/31/1995 | US5386573 Single chip microcomputer with interrupt processing capability during hold states |
01/31/1995 | US5386567 Hot removable and insertion of attachments on fully initialized computer systems |
01/31/1995 | US5386560 Execution of page data transfer by PT processors and issuing of split start and test instructions by CPUs coordinated by queued tokens |
01/31/1995 | US5386548 Method for storing data from an external processor in storage devices through buffer devices |
01/31/1995 | US5386541 Method of copying system data and copying adaptor therefor |
01/31/1995 | US5386540 Method and apparatus for transferring data within a computer using a burst sequence which includes modified bytes and a minimum number of unmodified bytes |
01/31/1995 | US5386539 IC memory card comprising an EEPROM with data and address buffering for controlling the writing/reading of data to EEPROM |
01/31/1995 | US5386535 Protected electronic mass memory unit including first and second buses of the parallel type |
01/31/1995 | US5386532 Method and apparatus for transferring data between a memory and a plurality of peripheral units through a plurality of data channels |
01/31/1995 | US5386518 Reconfigurable computer interface and method |
01/31/1995 | US5386517 Dual bus communication system connecting multiple processors to multiple I/O subsystems having a plurality of I/O devices with varying transfer speeds |
01/31/1995 | US5386514 Queue apparatus and mechanics for a communications interface architecture |
01/31/1995 | US5386503 Method for controlling window displays in an open systems windows environment |
01/31/1995 | US5386420 Coding method for correction and detection of skewed transitions in parallel asynchronous communication systems |
01/31/1995 | US5386412 Telecommunication system protocol for asynchronous data communication between multiport switch control processor and information support personal computer terminal |
01/31/1995 | US5386393 Fencing circuit and method for isolating spurious noise at system interface |
01/31/1995 | US5386385 Method and apparatus for preventing invalid operating modes and an application to synchronous memory devices |
01/31/1995 | CA2129065A1 Multi-channel data receiver system |
01/31/1995 | CA2051871C Control system for mediating service requests |
01/26/1995 | WO1995002866A1 Communication bus system with mitigation of slave station locking problem |
01/25/1995 | EP0635791A2 Data bus controller having a level setting circuit |
01/25/1995 | EP0635781A1 User interface having simultaneously movable tools and cursor |
01/25/1995 | EP0635780A1 User interface having clicktrough tools that can be composed with other tools |
01/25/1995 | EP0635779A1 User interface having movable sheet with click-through tools |
01/25/1995 | EP0635192A1 Circuit board connections |
01/25/1995 | EP0635150A1 Universal bus motherboard using a universal-to-specific bus translator card |
01/25/1995 | EP0576546A4 Networked variables. |
01/24/1995 | US5384808 Method and apparatus for transmitting NRZ data signals across an isolation barrier disposed in an interface between adjacent devices on a bus |
01/24/1995 | US5384805 RF communication systems in open architecture bus lines |
01/24/1995 | US5384783 Network system and line switching method used therein |
01/24/1995 | US5384773 Multi-media analog/digital/optical switching apparatus |
01/24/1995 | US5384697 Networked facilities management system with balanced differential analog control outputs |
01/24/1995 | US5384563 Method and apparatus for time synchronization of bus type local area networks including hierarchical networks |
01/19/1995 | WO1995002281A1 Automatic scsi termination circuit |
01/19/1995 | WO1995002223A1 Memory control device for an assay apparatus |
01/19/1995 | WO1995002219A1 System and method for distributed computation based upon movement, execution and interaction of processes in a network |
01/19/1995 | DE4424511A1 Method and device for operating data networks |
01/19/1995 | DE4420451A1 Inhibiting (blocking) mechanism for a CHECK-IN/CHECK-OUT model |
01/19/1995 | DE4323282A1 Method and circuit arrangement for the synchronisation of the data transmission between a transmitter and a receiver with the aid of a memory |
01/19/1995 | CA2483828A1 System and method for distributed computation based upon movement, execution, and interaction of processes in a network |
01/19/1995 | CA2166804A1 Memory control device for an assay apparatus |
01/18/1995 | EP0634857A2 Multimedia communication terminal |
01/18/1995 | EP0634723A1 Card coupler plug (CCP) for a card interface unit (CIU) |
01/18/1995 | EP0634722A2 Universal asynchronous receiver/transmitter |
01/18/1995 | EP0634719A2 System and method for distributed computation based upon the movement, execution, and interaction of processes in a network |
01/18/1995 | EP0634718A2 Computer systems integration |
01/18/1995 | EP0634716A1 Low-level direct connect protocol for PCL printers |
01/17/1995 | US5383191 Dual ring reconfiguration switching unit |
01/17/1995 | US5383185 Method and apparatus for data collision detection in a multi-processor communication system |
01/17/1995 | US5383182 Resequencing device for a node of a cell switching system |
01/17/1995 | US5382841 Switchable active bus termination circuit |
01/17/1995 | CA2001068C Method for transmitting data on the internal bus of a workstation, internal bus device implementing said method and matching circuit for said internal bus |
01/14/1995 | CA2127831A1 Method of controlling access to a buffer as well as apparatus for temporarily storing data packets and exchange with such apparatus |
01/12/1995 | WO1995001604A1 Intelligent communication system |
01/12/1995 | WO1995001603A1 Method and apparatus for performing bus transactions in a computer system |
01/12/1995 | WO1995001601A1 High-speed cpu interconnect bus architecture |
01/12/1995 | DE4423827A1 Cable management system for a computer |
01/12/1995 | DE4422786A1 Memory system |
01/11/1995 | EP0633532A1 Arrangement for decentralised control of bus access for units connected to a bus |
01/11/1995 | EP0633528A2 Maintenance of a data processing system |
01/11/1995 | EP0632913A1 Fiber optic memory coupling system |
01/10/1995 | US5381552 Programmable system for prioritizing and collecting central processor unit interrupts |
01/10/1995 | US5381551 Semiconductor integrated circuit including an arbitrate circuit for giving priority to a plurality of request signals |
01/10/1995 | US5381549 Information processing apparatus |
01/10/1995 | US5381543 Processor system with dual clock |
01/10/1995 | US5381541 Computer system having planar board with single interrupt controller and processor card with plural processors and interrupt director |
01/10/1995 | US5381540 Interface: interrupt masking with logical sum and product options |
01/10/1995 | US5381538 DMA controller including a FIFO register and a residual register for data buffering and having different operating modes |
01/10/1995 | US5381529 Shift register with dual clock inputs for receiving and sending information between I/O channels and host based on external and internal clock inputs respectively |
01/10/1995 | US5381414 Method and apparatus for determining if a data packet is addressed to a computer within a network |
01/10/1995 | US5381346 Virtual data source for a radio transceiver |
01/07/1995 | CA2127081A1 Processor interface chip for dual-microprocessor processor system |
01/07/1995 | CA2126743A1 Programmable error-checking matrix for digital communication system |
01/05/1995 | WO1995001028A1 High speed dominant mode bus for differential signals |
01/05/1995 | WO1995001027A1 New d2b device address initialisation by majority vote |
01/05/1995 | WO1995001026A1 New d2b device address initialisation starts with previous address |
01/05/1995 | WO1995000909A1 Expandable, partitionable, low overhead data processing system |
01/05/1995 | WO1995000908A1 A high speed/low overhead bus arbitration apparatus and method for arbitrating a system bus |
01/05/1995 | WO1994025914A3 Symmetric multiprocessing system with unified environment and distributed system functions |
01/05/1995 | DE4422189A1 Semiconductor-memory control unit |
01/04/1995 | EP0632673A2 Multimedia resource reservation system |
01/04/1995 | EP0632671A2 Method and apparatus for reserving system resources to ensure quality of service |
01/04/1995 | EP0632629A1 Modem with firmware upgrade feature |
01/04/1995 | EP0632628A2 Communication data processor |