Patents
Sitemap › H03 - Basic electronic circuitry › H03L - Automatic control, starting, synchronisation, or stabilisation of generators of electronic oscillations or pulses › H03L 7 - Automatic control of frequency or phase; Synchronisation
Patents for H03L 7 - Automatic control of frequency or phase; Synchronisation (37,643)
11/2003
11/27/2003US20030219082 Demodulation apparatus and receiving apparatus
11/27/2003US20030218953 Apparatus for detecting and correcting wobble error and phase locked loop circuit using the same
11/27/2003US20030218693 Broadcasting receiver
11/27/2003US20030218511 Oscillator and PLL circuit using the same
11/27/2003US20030218510 Self-regulating voltage controlled oscillator
11/27/2003US20030218509 Phase locked loop for recovering a clock signal from a data signal
11/27/2003US20030218486 Digital DLL apparatus for correcting duty cycle and method thereof
11/27/2003US20030218485 Charge-pump circuit for charge-share suppression
11/27/2003US20030218483 Synchronous circuit
11/26/2003EP1222740B1 Phase-locking loop
11/26/2003EP1166447B1 Method and apparatus for reducing oscillator noise by noise-feedforward
11/26/2003EP1048110B1 A post-filtered sigma-delta for controlling a phase locked loop modulator
11/26/2003CN1129231C Power-consumption reduced over-sampling clock restore circuit and method for regulating clock signal phase
11/25/2003US6654899 Tracking bin split technique
11/25/2003US6654413 Phase synchronization method for extended partial response, and phase synchronization circuit and read channel circuit using this method
11/25/2003US6653907 Frequency-variable RC oscillator and microcomputer
11/25/2003US6653876 Method and apparatus for synthesizing a clock signal using a compact and low power delay locked loop (DLL)
11/25/2003US6653875 Method and apparatus for a delay lock loop
11/25/2003US6653874 Clock producing circuit capable of suppressing phase shift at a time of change from active clock to standby clock
11/20/2003WO2003085831A3 A method and apparatus for precise signal interpolation
11/20/2003WO2003063357A3 Methods and apparatuses for tuning voltage controlled oscillators
11/20/2003WO2003013001A3 Clock data recovering system with external early/late input
11/20/2003WO2002052728A3 Synthesizer with lock detector, lock algorithm, extended range vco, and a simplified dual modulus divider
11/20/2003US20030216130 Phase locking loop frequency synthesiser
11/20/2003US20030215045 Self-adjustment device in PLL frequency synthesizer and method thereof
11/20/2003US20030215044 Data-directed frequency-and-phase lock loop
11/20/2003US20030215043 PLO device
11/20/2003US20030215042 Adjustment and calibration system for post-fabrication treatment of phase locked loop input receiver
11/20/2003US20030215041 Method and apparatus to store delay locked loop biasing parameters
11/20/2003US20030215040 Delay locked loop with frequency control
11/20/2003US20030215039 Digital multi-phase clock generator
11/20/2003US20030214362 Method and apparatus for calibration of a post-fabrication bias voltage tuning feature for self biasing phase locked loop
11/20/2003US20030214360 Frequency synthesizer circuit
11/20/2003US20030214350 Data-directed frequency acquisition loop
11/20/2003US20030214339 Timing generation circuit and method for timing generation
11/20/2003US20030214338 Tunable delay circuit
11/20/2003US20030214335 Clock and data recovery circuit and clock control method thereof
11/20/2003US20030214334 Measure-controlled circuit with frequency control
11/20/2003US20030214333 Adjustment and calibration system for post-fabrication treatment of phase locked loop charge pump
11/20/2003US20030214332 Phase locked loop with low steady state phase errors and calibration circuit for the same
11/20/2003US20030214331 Digital phase-locked loop device for synchronizing signal and method for generating stable synchronous signal
11/20/2003US20030214330 Phase-locked loop circuit
11/20/2003US20030214280 Method and apparatus for calibrating a delay locked loop charge pump current
11/20/2003DE19939036C2 Anordnung zum Wobbeln (Sweepen) eines Frequenzsynthesesizers Arrangement of sweeping (sweep) of Frequenzsynthesesizers
11/19/2003EP1363436A2 Synchronization of multicarrier symbols
11/19/2003EP1363399A2 Clock and data recovery circuit and clock control method thereof
11/19/2003EP1362413A2 Compensation method and compensating device for a pll circuit for two-point modulation
11/19/2003CN1457149A Encoding up/down based D-A converter and delayed phase locking loop device and method therefor
11/19/2003CN1128520C Clock reproduction circuit and elements used in the same
11/19/2003CN1128447C Automatic equalization system
11/18/2003US6651231 Clock synchronizing circuit and method of designing the same
11/18/2003US6651179 Delay time judging apparatus
11/18/2003US6650879 Personal communications device with GPS receiver and common clock source
11/18/2003US6650721 Phase locked loop with numerically controlled oscillator divider in feedback loop
11/18/2003US6650720 Phase lock loop and transconductance circuit for clock recovery
11/18/2003US6650719 MPEG PCR jitter, frequency offset and drift rate measurements
11/18/2003US6650699 Methods and apparatus for timing recovery from a sampled and equalized data signal
11/18/2003US6650196 Multi-frequency band controlled oscillator
11/18/2003US6650195 Oscillator with differential tunable tank circuit
11/18/2003US6650194 Phase shift control for voltage controlled oscillator
11/18/2003US6650193 Oscillator with a noise reduction function, a writer, and a method of controlling a writer
11/18/2003US6650187 Decision directed suppressed carrier symbol-rate PLL with programmable phase discriminator and chip-rate phase extrapolation
11/18/2003US6650186 Clock pulse and data regenerator for different data rates
11/18/2003US6650160 Two step variable length delay circuit
11/18/2003US6650159 Method and apparatus for precise signal interpolation
11/18/2003US6650157 Using a push/pull buffer to improve delay locked loop performance
11/18/2003US6650156 Integrated circuit charge pumps having control circuits therein that inhibit parasitic charge injection from control signals
11/18/2003US6650146 Digital frequency comparator
11/18/2003US6648744 Method and apparatus for tenderizing meat
11/13/2003WO2003094377A1 Frequency synthesizers for supporting voice communication and wireless networking standards
11/13/2003WO2003028106A3 Rf circuits including transistors having strained material layers
11/13/2003US20030212930 Clock data recovery circuitry associated with programmable logic device circuitry
11/13/2003US20030210815 Noise reduction through comparative histograms
11/13/2003US20030210758 Recovered clock generator with high phase resolution and recovered clock generating method
11/13/2003US20030210602 Delay locked loop for use in synchronous dynamic random access memory
11/13/2003US20030210099 High-speed, high PSRR, wide operating range voltage controlled oscillator
11/13/2003US20030210098 Phase locked loop circuit having automatic adjustment for free-running frequency of voltage controlled oscillator
11/13/2003US20030210083 Speed-locked loop to provide speed information based on die operating conditions
11/13/2003US20030210082 Generation of synchronized clocks to multiple locations in a system
11/13/2003CA2484194A1 Frequency synthesizers for supporting voice communication and wireless networking standards
11/12/2003EP1361661A2 Digital to analog converter, delay-locked loop, memory device and counting method
11/12/2003EP1360791A1 Direct digital synthesizer based on delay line with sorted taps
11/12/2003EP1360768A2 Sigma-delta programming device for a pll-frequency synthesizer
11/12/2003EP1360569A2 Timing control means for automatic compensation of timing uncertainties
11/12/2003CN2586300Y Loran time coding emitting controller
11/12/2003CN1455513A Phase-locked loop circuit of eliminating self-shaking in signals received by control circuit
11/12/2003CN1127812C Compensation for phase errors caused by clock jitter in CDMA communication system
11/12/2003CN1127803C Bit synchronizing circuit having high synchronization characteristics
11/11/2003US6647081 Phase-locked loop (PLL) circuit for selectively correcting clock skew in different modes
11/11/2003US6647080 Carrier phase initialization with sub-LSB accuracy
11/11/2003US6646964 Harmonic correction in phase-locked loops
11/11/2003US6646512 Self-bias and differential structure based PLL with fast lockup circuit and current range calibration for process variation
11/11/2003US6646484 PLL circuit including a control logic circuit for adjusting the delay times of the clocks so that the phase error of the clocks is reduced
11/11/2003US6646483 Output buffer circuit for reducing variation of slew rate due to variation of PVT and load capacitance of output terminal, and semiconductor device including the same
11/11/2003US6646480 Glitchless clock output circuit and the method for the same
11/11/2003US6644083 Spin forming a tubular workpiece to form a radial flange on a tubular flange and a bead or thick rim on the radial flange
11/06/2003WO2003092249A2 Controlling output power in cellular telephones
11/06/2003WO2003092162A1 A synchronization signal processor
11/06/2003WO2003019783A3 Phase-locked loop with analog phase rotator
11/06/2003WO2003017493A3 Differential charge pump
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