Patents
Sitemap › H03 - Basic electronic circuitry › H03L - Automatic control, starting, synchronisation, or stabilisation of generators of electronic oscillations or pulses › H03L 7 - Automatic control of frequency or phase; Synchronisation
Patents for H03L 7 - Automatic control of frequency or phase; Synchronisation (37,643)
05/2003
05/15/2003WO2003041312A1 Digital audio broadcast devices
05/15/2003WO2003041277A2 A communication semiconductor integrated circuit device and a wireless communication system
05/15/2003WO2003041276A2 Cascaded delay locked loop circuit
05/15/2003WO2003040915A1 Method for implementing of wait-states
05/15/2003WO2003040902A1 Semiconductor integrated circuit device, system and signal transmission method
05/15/2003WO2003040900A2 Clocking and synchronization circuitry
05/15/2003WO2002037683A3 Phase lock loop circuit
05/15/2003US20030092409 Tuner comprising a voltage converter
05/15/2003US20030091139 System and method for adjusting phase offsets
05/15/2003US20030091138 Data clock regenerating apparatus
05/15/2003US20030090952 Delayed locked loop implementation in a synchronous dynamic random access memory
05/15/2003US20030090333 Temperature-compensated radio-frequency oscillator and communication device
05/15/2003US20030090330 Voltage controlled oscillation circuit having easily controllable oscillation characteristic and capable of generating high frequency and low frequency internal clocks
05/15/2003US20030090327 High-speed and high-precision phase locked loop
05/15/2003US20030090305 Clock shaping circuit and electronic equipment
05/15/2003US20030090296 Apparatus for ensuring correct start-up and phase locking of delay locked loop
05/14/2003EP1311068A1 Method of and apparatus for detecting difference between frequencies, and phase locked loop circuit
05/14/2003EP1311066A2 Apparatus and method for delay matching of full and divided clock signals
05/14/2003EP1311065A1 Tuner comprising a voltage converter
05/14/2003EP1309913A2 Efficient clock start and stop apparatus for clock forwarded sytem i/o
05/14/2003CN1418404A Clock generation circuit and integrated circuit for reproducing an audio signal comprsing such a clock generation circuit
05/14/2003CN1418403A Adjustable spread spectrum clock generator and method thereof
05/14/2003CN1418402A Phase detetor
05/14/2003CN1417953A Frequency converter circuit
05/14/2003CN1417949A Digital phase-locked loop
05/14/2003CN1417948A Data restoring circuit and relevant method
05/14/2003CN1108662C PLL circuit
05/13/2003US6564359 Clock control circuit and method
05/13/2003US6564350 Testing frequency hopping devices
05/13/2003US6564039 Frequency generation circuit and method of operating a tranceiver
05/13/2003US6563897 Multirate symbol timing recovery circuit
05/13/2003US6563484 Apparatus and method for processing synchronizing signal of monitor
05/13/2003US6563389 Phase locked loop with charge injection cancellation
05/13/2003US6563388 Timing loop bandwidth tracking data rate
05/13/2003US6563387 Method and apparatus for synthesizing high-frequency signals for wireless communications
05/13/2003US6563386 Self-starter for PLL synthesizers
05/13/2003US6563355 Recovery circuit generating low jitter reproduction clock
05/13/2003US6563354 On-chip circuit to compensate output drive strength across process corners
05/08/2003WO2003039063A2 Timing recovery with varaible bandwidth phase locked loop and non-linear control paths
05/08/2003WO2003039045A2 Method and apparatus for providing multiple spread spectrum clock generator circuits with overlapping output frequencies
05/08/2003WO2003039004A1 Timing jitter frequency detector for timing recovery systems
05/08/2003WO2003039003A1 Method and architecture for self-clocking digital delay locked loop
05/08/2003WO2003039002A2 Fractional-r- frequency synthesizer
05/08/2003US20030088834 Semiconductor integrated circuit device
05/08/2003US20030088801 Implementation of wait-states
05/08/2003US20030087619 Frequency conversion circuit having a low phase noise
05/08/2003US20030086519 Dual steered frequency synthesizer
05/08/2003US20030086518 Clock recovery from data streams containing embedded reference clock values
05/08/2003US20030086348 Optical disk device
05/08/2003US20030086339 Digital clock recovery circuit
05/08/2003US20030085768 Phase locked loop reconfiguration
05/08/2003US20030085766 Tunable oscillator
05/08/2003US20030085744 Delay locked loop circuit and method having adjustable locking resolution
05/08/2003US20030085743 Phase locked loop circuit
05/08/2003US20030085742 Clocking and synchronization circuitry
05/08/2003US20030085739 Method of and apparatus for detecting difference between frequencies, and phase locked loop circuit
05/07/2003EP1309123A2 Ultrahigh-speed clock extraction circuit for optical signals
05/07/2003EP0988691A4 Frequency synthesis circuit tuned by digital words
05/07/2003CN1416215A Oscillator and electronic instrument using same
05/06/2003US6560661 Data receiver that performs synchronous data transfer with reference to memory module
05/06/2003US6560306 Phase locked loop (PLL) with linear parallel sampling phase detector
05/06/2003US6560305 Frequency detector
05/06/2003US6560302 Sync detection device for an optical disk player and method for detecting sync
05/06/2003US6560053 Clock recovery apparatus
05/06/2003US6560007 Bit-phase synchronized optical pulse stream local generator
05/06/2003US6559726 Multi-modulus counter in modulated frequency synthesis
05/06/2003US6559725 Phase noise reduction system for frequency synthesizer and method thereof
05/06/2003US6559698 Spread spectrum type clock generating circuit
05/06/2003US6559697 Multiplied clock generating circuit
05/06/2003US6559696 Circuit arrangement for generating a clock-pulse signal having a frequency synchronous with a reference clock-pulse signal
05/06/2003US6559694 Timing signal occurrence circuit
05/02/2003EP1262023A4 Method and apparatus for providing a clock generation circuit for digitally controlled frequency or spread spectrum clocking
05/02/2003EP1221221B1 Clock pulse and data regenerator for different data rates
05/02/2003EP0947050B1 A digital phase-locked loop and a method of controlling it, as well as a method and receiver circuit for desynchronization in a digital transmission system
05/02/2003EP0843417B1 Phase locked loop circuit
05/01/2003WO2003036886A2 Method and system for transferring ip packets by aggregating multiple wireless communication channels for high data rate transfers
05/01/2003WO2003036796A1 Phase-locked loop circuit, delay locked loop circuit, timing generator, semiconductor test instrument, and semiconductor integrated circuit
05/01/2003WO2003036314A1 Timing generator, semiconductor testing device, and timing generating method
05/01/2003US20030084362 Method and apparatus for generating and synchronizing multiple clocks
05/01/2003US20030083834 Timing jitter frequency detector for timing recovery systems
05/01/2003US20030081709 Single-ended IO with dynamic synchronous deskewing architecture
05/01/2003US20030081653 Method and apparatus for providing multiple spread spectrum clock generator circuits with overlapping output frequencies
05/01/2003US20030081582 Aggregating multiple wireless communication channels for high data rate transfers
05/01/2003US20030081473 System and method for skew compensating a clock signal and for capturing a digital signal using the skew compensated clock signal
05/01/2003US20030081472 System and method for skew compensating a clock signal and for capturing a digital signal using the skew compensated clock signal
05/01/2003US20030080818 Fast-acquisition phase-locked loop
05/01/2003US20030080817 PLL frequency synthesizer using charge pump
05/01/2003US20030080794 Device and method for clock generation
05/01/2003US20030080791 Method and architecture for self-clocking digital delay locked loop
05/01/2003CA2464409A1 Method and system for transferring ip packets by aggregating multiple wireless communication channels for high data rate transfers
04/2003
04/30/2003DE4245020C2 Swept RF and microwave frequency synthesised source
04/30/2003DE10016853C2 Verzögerungstakt-Erzeugungsvorrichtung Delay clock generating apparatus
04/30/2003CN1415137A Zero-delay buffer circuit for spread spectrum clock system and method
04/30/2003CN1107373C Frequency lock indicator of FPLL demodulated signal having a pilot
04/29/2003US6557117 Built-in self test for PLL module with on-chip loop filter
04/29/2003US6556643 Majority filter counter circuit
04/29/2003US6556640 Digital PLL circuit and signal regeneration method
04/29/2003US6556637 Semiconductor device having decision feedback equalizer
04/29/2003US6556592 Correction method for clock synchronization with ISDN in cell station for use in private-network-use PHS and a circuit therefor
04/29/2003US6556488 Delay locked loop for use in semiconductor memory device
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