Patents
Patents for H03K 5 - Manipulating pulses not covered by one of the other main groups in this subclass (25,714)
09/2005
09/08/2005US20050195010 Time-delay circuit
09/08/2005US20050195009 Commutating phase selector
09/08/2005US20050195004 Delay locked loop in semiconductor memory device and its clock locking method
09/08/2005US20050194997 Amplitude limiting circuit
09/08/2005US20050194996 Polarity-insensitive signal detect circuit for use with any signal sequence
09/08/2005DE10393465T5 Stromintegrierender Leseverstärker für Speichermodule bei der RFID Integrating current sense amplifier for memory modules in the RFID
09/08/2005DE10130123B4 Verzögerungsregelkreis zur Erzeugung komplementärer Taktsignale Delay-locked loop for generating complementary clock signals
09/07/2005EP1571530A1 Frequency modulator apparatus of phase selection type, and frequency synthesizer of phase selection type
09/07/2005CN1666416A Active continuous-time filter with increased dynamic range in the presence of blocker signals
09/07/2005CN1666290A Methods and apparatus for delay circuit
09/07/2005CN1665135A Delay signal generator circuit and memory system including the same
09/07/2005CN1664956A Delay locked loop in semiconductor memory device and its clock locking method
09/07/2005CN1218324C Register and signal generating method suitable for wide band
09/06/2005US6940937 Scalable high-speed precision frequency and phase synthesis
09/06/2005US6940763 Clock synchronous type semiconductor memory device
09/06/2005US6940340 Noise-proof bus circuit
09/06/2005US6940331 Delayed tap signal generating circuit for controlling delay by interpolating two input clocks
09/06/2005US6940330 Timing generator, semiconductor test apparatus, and timing generating method
09/06/2005US6940329 Hysteresis circuit used in comparator
09/06/2005US6940328 Methods and apparatus for duty cycle control
09/06/2005US6940327 Pulse width control circuit controlling pulse width of output light
09/06/2005US6940318 Accurate voltage comparator with voltage-to-current converters for both reference and input voltages
09/06/2005US6940316 Comparator circuit
09/01/2005WO2005081449A1 Analog to digital converter clock synchronizer
09/01/2005WO2005081404A1 Pulse wave radar apparatus
09/01/2005WO2005081403A1 Phase adjusting circuit for minimizing irregularities at phasesteps
09/01/2005US20050190831 Digital filter enabling consecutive readout of filter coefficients from a continuous sequence of storage locations during convolution calculation
09/01/2005US20050189979 Clock signal generation circuits and methods using phase mixing of even and odd phased clock signals
09/01/2005US20050189978 Clock generator with programmable non-overlapping-clock-edge capability
09/01/2005US20050189977 Double-edge-trigger flip-flop
09/01/2005US20050189961 Method and apparatus for signal reception using ground termination and/or non-ground termination
09/01/2005US20050189605 Integrated circuit logic with self compensating shapes
09/01/2005US20050189604 Integrated circuit logic with self compensating block delays
09/01/2005DE102004015318B3 Input stage for electronic circuit for receiving, evaluating input signal, passing to subsequent stage has control circuit that activates one or other receiving stage depending on current drains of both stages for respective input signal
09/01/2005DE102004007172A1 Phaseneinstellungsschaltung für minimale Unregelmäßigkeiten bei Phasenschritten Phase adjustment circuit for minimum irregularities in phase steps
08/2005
08/31/2005EP1568044A2 Power converter circuitry and method
08/31/2005CN1661919A Operation mode setting circuit
08/31/2005CN1661918A Clock duty ratio correction circuit
08/31/2005CN1661914A Automatic time constant adjustment circuit
08/31/2005CN1661602A Integrated circuit logic with self compensating block delays
08/31/2005CN1217486C Semiconductor integrated circuit
08/31/2005CN1217485C CMOS circuit with constant output swing and variable time delay for voltage controlled oscillator
08/31/2005CN1217484C Pulse amplitude analyzer
08/30/2005US6937953 Circuit configuration for receiving at least two digital signals
08/30/2005US6937681 Skew correction apparatus
08/30/2005US6937672 Determining the position of a constant frequency interval in a telecommunication signal
08/30/2005US6937530 Delay locked loop “ACTIVE Command” reactor
08/30/2005US6937485 Duty ratio detecting apparatus with small return time
08/30/2005US6937174 Sampling/holding method and circuit
08/30/2005US6937089 Offset, delay and parasitically immune resister-capacitor (RC) tracking loop and method of using same
08/30/2005US6937086 Method and apparatus for operating a field-effect transistor (FET) pair
08/30/2005US6937084 Processor with dual-deadtime pulse width modulation generator
08/30/2005US6937082 Information processing apparatus with clock generating circuit and information processing apparatus with clock delaying circuit
08/30/2005US6937081 Delay producing method, delay adjusting method based on the same, and delay producing circuit and delay adjusting circuit applied with them
08/30/2005US6937078 Circuit configuration for regenerating clock signals
08/25/2005WO2005078927A1 Bit rate determination circuit based on low bit rate signal
08/25/2005WO2005078735A1 Semiconductor memory
08/25/2005WO2005078734A1 Dll circuit
08/25/2005US20050185709 Apparatus and method for digitally filtering spurious transitions on a digital signal
08/25/2005US20050185449 Nonvolatile data storage apparatus
08/25/2005US20050184798 Comparator
08/25/2005US20050184792 High voltage switch circuit for semiconductor device
08/25/2005US20050184788 Logic level voltage translator
08/25/2005US20050184787 Delay circuit
08/25/2005US20050184786 Automatic time constant adjustment circuit
08/25/2005US20050184785 Combined sample data delay compensation system
08/25/2005US20050184782 Differential input receiver
08/25/2005US20050184781 Duty adjustment circuit
08/25/2005US20050184780 Clock duty ratio correction circuit
08/25/2005US20050184779 Open-loop digital duty cycle correction circuit without DLL
08/25/2005US20050184778 Apparatus and method for increasing the performance of a clock-based digital pulse width modulation generator
08/25/2005US20050184777 Method and apparatus for an improved timer circuit and pulse width detection
08/25/2005US20050184776 System and method for implementing a micro-stepping delay chain for a delay locked loop
08/25/2005US20050184775 System and method for implementing a micro-stepping delay chain for a delay locked loop
08/25/2005US20050184764 Method and apparatus for detecting on-die voltage variations
08/25/2005US20050184763 Signal transmission circuit
08/25/2005US20050184762 Comparator and AD conversion circuit having hysteresis circuit
08/25/2005US20050184761 Comparator circuit
08/25/2005DE102004004091A1 Vorrichtung zur Verwendung bei der Synchronisation von Taktsignalen, sowie Taktsignal-Synchronisationsverfahren Apparatus for use in the synchronization of clock signals, and clock signal synchronization method
08/24/2005EP1566888A1 Clock-pulse generator circuit
08/24/2005CN1659780A Decision feedback equalizer
08/24/2005CN1658510A Comparator and ad conversion circuit having hysteresis circuit
08/24/2005CN1658504A Method for obtaining silicon controlled zero cross synchonous sigual and trigger control
08/24/2005CN1216324C Multiphase clock generating circuit
08/23/2005US6934871 Programmable counters for setting bus arbitration delays involves counting clock cycles equal to a count number loaded from a memory
08/23/2005US6934674 Clock generation and distribution in an emulation system
08/23/2005US6934215 Semiconductor memory device having duty cycle correction circuit and interpolation circuit interpolating clock signal in the semiconductor memory device
08/23/2005US6933762 DC offset cancellation circuit, differential amplification circuit with DC offset cancellation circuit, photo-electric pulse conversion circuit, pulse shaping circuit, and pulse generation circuit
08/23/2005US6933761 Techniques for dynamically selecting phases of oscillator signals
08/23/2005US6933759 Systems and methods of performing duty cycle control
08/23/2005US6933758 Synchronous mirror delay circuit with adjustable locking range
08/23/2005US6933754 Clock gated power supply noise compensation
08/23/2005US6933753 Sensor signal output circuit
08/23/2005US6933750 Buffer circuit, buffer tree, and semiconductor device
08/18/2005WO2005076464A1 System and method for frequency translation with harmonic suppression using mixer stages
08/18/2005WO2005013489A3 Delay matching for clock distribution in a logic circuit
08/18/2005US20050180498 High speed decision feedback equalizer
08/18/2005US20050180497 Adaptive digital filter
08/18/2005US20050179479 Clock distribution network with process, supply-voltage, and temperature compensation
08/18/2005US20050179478 Device to be used in the synchronization of clock pulses, as well as a clock pulse synchronization process