| Patents for H03K 5 - Manipulating pulses not covered by one of the other main groups in this subclass (25,714) |
|---|
| 01/05/2006 | WO2006002355A2 Comparator feedback peak detector |
| 01/05/2006 | WO2006002316A1 Input enable/disable circuit |
| 01/05/2006 | WO2006000088A2 Transmit signal generator and method |
| 01/05/2006 | US20060004898 Circuit configuration for averaging |
| 01/05/2006 | US20060002492 DC-offset compensation |
| 01/05/2006 | US20060001750 Differential comparator, analog/digital conversion apparatus and imaging apparatus |
| 01/05/2006 | US20060001482 Filter device |
| 01/05/2006 | US20060001477 High voltage generator |
| 01/05/2006 | US20060001455 Circuit and method for performing track and hold operations |
| 01/05/2006 | US20060001454 Microcode-initiated high speed comparator |
| 01/05/2006 | US20060001453 Method to implement hysteresis in a MOSFET differential pair input stage |
| 01/05/2006 | US20060001446 Duty cycle controlled CML-CMOS converter |
| 01/05/2006 | DE102005026195A1 Komparator und Verfahren zum Verstärken eines Eingangsignals Comparator and method for amplifying an input signal |
| 01/05/2006 | DE102004027655A1 Control unit, especially for brake light of vehicle, has timing pulse processing circuit which processes timing pulse signal so that it transmits signal for inactive state if timing pulse signal does not change inside time interval |
| 01/05/2006 | DE10102887B4 Verzögerungsvorrichtung, die eine Verzögerungssperrschleife aufweist und Verfahren zum Kalibrieren derselben Delay means having a delay lock loop and method of calibrating same |
| 01/04/2006 | EP1612993A1 Method and arrangement for changing the operation mode of an agent of a management network |
| 01/04/2006 | EP1612936A2 Device for clock control |
| 01/04/2006 | EP1612762A2 Semiconductor integrated circuit, drive circuit, and plasma display apparatus |
| 01/04/2006 | EP1611682A1 Method for optimizing a dsp input clock using a comparing/analyzing circuit |
| 01/04/2006 | CN1717868A Phase comparison circuit and CDR circuit |
| 01/04/2006 | CN1716774A Pulse width modulation circuit |
| 01/04/2006 | CN1716773A Differential comparator, analog/digital conversion apparatus and imaging apparatus |
| 01/04/2006 | CN1716772A Gate clock circuit and relative method |
| 01/04/2006 | CN1716771A Clock control cell |
| 01/04/2006 | CN1716214A Decision feedback equalization input buffer |
| 01/03/2006 | US6982585 Pulse shaping system, laser printer, pulse shaping method and method of generating serial video data for laser printer |
| 01/03/2006 | US6982581 Duty cycle correction circuit |
| 01/03/2006 | US6982575 Clock ratio data synchronizer |
| 12/29/2005 | WO2005125010A1 Electronic device for generating synchronisation signals |
| 12/29/2005 | US20050289379 System and method for producing precision timing signals |
| 12/29/2005 | US20050286672 Phase splitter using digital delay locked loops |
| 12/29/2005 | US20050286652 Transmit signal generator and method |
| 12/29/2005 | US20050286626 Method for adjusting parameters of equalizer |
| 12/29/2005 | US20050286623 Adaptive filter structure with two adaptation modes |
| 12/29/2005 | US20050286505 Method and apparatus for generating a phase dependent control signal |
| 12/29/2005 | US20050285819 Semiconductor integrated circuit, drive circuit, and plasma display apparatus |
| 12/29/2005 | US20050285779 Method of and apparatus for increasing the peak output pulse power delivered by capacitor-driven high-power diode and square-loop saturable reactor pulse compression generators with the aid of minority carrier sweep-out circuits within the pulse compression circuit |
| 12/29/2005 | US20050285698 Impedance control circuits and methods of controlling impedance |
| 12/29/2005 | US20050285659 Semiconductor device |
| 12/29/2005 | US20050285653 High speed fully scaleable, programmable and linear digital delay circuit |
| 12/29/2005 | US20050285652 Interpolator linearity testing system |
| 12/29/2005 | US20050285649 Duty cycle correction circuit for use in a semiconductor device |
| 12/29/2005 | US20050285648 Closed-loop independent DLL-controlled rise/fall time control circuit |
| 12/29/2005 | US20050285647 Closed-loop independent DLL-controlled rise/fall time control circuit |
| 12/29/2005 | US20050285646 Closed-loop control of driver slew rate |
| 12/29/2005 | US20050285637 CMOS LvPECL driver with output level control |
| 12/29/2005 | US20050285635 Voltage detection circuit |
| 12/29/2005 | US20050285634 Peak detector systems and methods with leakage compensation |
| 12/29/2005 | US20050285633 Comparator feedback peak detector |
| 12/29/2005 | US20050285627 Input enable/disable circuit |
| 12/29/2005 | DE102005018738A1 Verfahren zur Optimierung der Zeitsteuerung zwischen Signalen A method for optimizing the timing between signals |
| 12/29/2005 | DE102005010056A1 Rücksetzschaltungsanordnung für eine integrierte Schaltung Reset circuitry for an integrated circuit |
| 12/29/2005 | DE102004055036B3 Verstärkerschaltung und Verfahren zur Korrektur des Tastverhältnisses eines differentiellen Taktsignals Amplifier circuit and method for correcting the duty cycle of a differential clock signal |
| 12/29/2005 | DE102004009038B4 Verfahren und Anordnung zur Reduktion eines dynamischen Offsets bei der Verarbeitung unsymmetrischer Signalfolgen Method and apparatus for reducing a dynamic offsets in the processing of asymmetric signal sequences |
| 12/28/2005 | EP1609242A2 High speed track and hold amplifier for direct digital down-conversion |
| 12/28/2005 | CN1713267A Methods and devices for obtaining sampling clocks |
| 12/27/2005 | US6981185 Methods and apparatus to correct duty cycle |
| 12/27/2005 | US6981168 Clock data recovery system |
| 12/27/2005 | US6980041 Non-iterative introduction of phase delay into signal without feedback |
| 12/27/2005 | US6980040 Delay adjusting apparatus providing different delay times by producing a plurality of delay control signals |
| 12/27/2005 | US6980036 Semiconductor device comprising frequency multiplier of external clock and output buffer of test data and semiconductor test method |
| 12/27/2005 | US6980023 Dynamically adjustable signal detector |
| 12/27/2005 | US6979995 Frequency measuring circuit and resonant pressure sensor type differential pressure/pressure transmitter using the frequency measuring unit |
| 12/22/2005 | WO2005122398A2 Lateral drift vertical metal-insulator semiconductors |
| 12/22/2005 | US20050283336 Process independent delay chain |
| 12/22/2005 | US20050282511 Frequency multiply circuit using SMD, with arbitrary multiplication factor |
| 12/22/2005 | US20050281364 Power and area efficient adaptive equalization |
| 12/22/2005 | US20050281327 Hierarchical adaptive equalizer and design method thereof |
| 12/22/2005 | US20050280459 Flip-flop circuit |
| 12/22/2005 | US20050280458 Low power PLL for PWM switching digital control power supply |
| 12/22/2005 | US20050280454 Signal processing circuit |
| 12/22/2005 | US20050280452 Interpolator testing system |
| 12/22/2005 | US20050280447 Low voltage selection control circuit for dual power supply systems |
| 12/22/2005 | US20050280442 Semiconductor integrated circuit |
| 12/22/2005 | US20050280437 Apparatus and methods for adjusting performance of integrated circuits |
| 12/22/2005 | DE19983138B4 Verfahren und Vorrichtung zum Verändern einer Taktfrequenz auf einer Phase-zu-Phase-Basis Method and apparatus for changing a clock frequency to a phase-to-phase base |
| 12/21/2005 | EP1607754A1 Circuit for monitoring a load current |
| 12/21/2005 | EP1606877A1 Clock generator |
| 12/21/2005 | CN1711686A Method and apparatus to actively sink current in an integrated circuit with a floating i/o supply voltage |
| 12/21/2005 | CN1711683A Adaptive hysteresis for reduced swing signalling circuits |
| 12/21/2005 | CN1710814A Apparatus and method for monitoring input voltage |
| 12/21/2005 | CN1710813A SMT arbitrary multiplication circuit |
| 12/21/2005 | CN1710812A Flip-flop circuit |
| 12/21/2005 | CN1232984C Dynamically precharged current induction amplifier |
| 12/20/2005 | US6977977 Compensation of I/Q gain mismatch in a communications receiver |
| 12/20/2005 | US6977971 Digital data transmission system with device for correcting baseline wander |
| 12/20/2005 | US6977697 Method for manufacturing liquid crystal display device |
| 12/20/2005 | US6977538 Delay unit for periodic signals |
| 12/20/2005 | US6977536 Clock multiplier |
| 12/20/2005 | US6977532 Dual differential comparator circuit with full range of input swing |
| 12/20/2005 | US6977531 RF signal peak detector |
| 12/20/2005 | US6977530 Pulse shaper circuit for sense amplifier enable driver |
| 12/20/2005 | US6977529 Differential clock signal detection circuit |
| 12/20/2005 | US6977420 ESD protection circuit utilizing floating lateral clamp diodes |
| 12/15/2005 | WO2005099407A3 Apparatus for and method of developing equalized values from samples of a signal received from a channel |
| 12/15/2005 | US20050278675 General purpose delay logic |
| 12/15/2005 | US20050278132 PWM dual store protection |
| 12/15/2005 | US20050276145 Differential input buffer for receiving signals relevant to low power |
| 12/15/2005 | US20050276136 Method and apparatus for amplifying a regulated differential signal to a higher voltage |
| 12/15/2005 | US20050275459 Voltage comparator circuit |