Patents
Sitemap › H03 - Basic electronic circuitry › H03K - Pulse technique › H03K 5 - Manipulating pulses not covered by one of the other main groups in this subclass
Patents for H03K 5 - Manipulating pulses not covered by one of the other main groups in this subclass (25,714)
09/2005
09/29/2005US20050212575 Duty cycle correction circuit of delay locked loop and the delay locked loop having the duty cycle correction circuit
09/29/2005US20050212573 Clock distortion detector using a synchronous mirror delay circuit
09/29/2005US20050212568 Drive circuit and method of applying high voltage test thereon
09/29/2005US20050212559 Single-ended to differential conversion circuit with duty cycle correction
09/29/2005US20050212553 Method and apparatus for selectably providing single-ended and differential signaling with controllable impedence and transition time
09/29/2005US20050211893 Time of flight system on a chip
09/29/2005DE4219790B4 Baustein zur Impulsformung Module for pulse shaping
09/28/2005EP1580920A1 Latch and phase synchronization circuit using same
09/28/2005EP1580893A1 Device and method for phase detection of a signal
09/28/2005EP1580881A2 High-frequency power amplifier and communication apparatus
09/28/2005EP1579483A2 System and method for expanding a pulse width
09/28/2005CN1675838A Synchronous mirror delay (SMD) circuit and method including a counter and reduced size bi-directional delay line
09/28/2005CN1675610A Clock generator for integrated circuit
09/28/2005CN1674437A 比较器电路 Comparator circuit
09/28/2005CN1220952C Dispersive bus terminal framework
09/27/2005US6950770 Method and apparatus for calibration of a delay element
09/27/2005US6950488 Delay locked-loop circuit for reducing load of variable delay unit at high-frequency operation and locking external clock signal stably
09/27/2005US6950487 Phase splitter using digital delay locked loops
09/27/2005US6950486 Delay apparatus and method
09/27/2005US6950485 Precision timing generator apparatus and associated methods
09/27/2005US6950479 DC offset compensation
09/27/2005US6949966 DLL circuit capable of preventing malfunctioning causing locking in an antiphase state
09/27/2005US6949965 Low voltage pull-down circuit
09/27/2005US6949956 General purpose delay logic
09/27/2005US6949955 Synchronizing signals between clock domains
09/22/2005WO2004112339A8 Decision feedback equalizer with combined cck encoding-decoding in feedback filtering
09/22/2005US20050208909 High-frequency power amplifier and communication apparatus
09/22/2005US20050207485 Pipelined adaptive decision feedback equalizer
09/22/2005US20050207484 Device and method for detecting the phase of a signal
09/22/2005US20050207076 Sub-circuit voltage manipulation
09/22/2005US20050206433 Apparatus for transferring various direct current voltage levels to digital output voltage levels
09/22/2005US20050206429 Clamp circuit device
09/22/2005US20050206427 Semiconductor integrated circuit device
09/22/2005US20050206426 Integrated circuit systems and devices having high precision digital delay lines therein
09/22/2005US20050206425 Delay circuit
09/22/2005US20050206422 Enable pin using programmable hysteresis improvement
09/22/2005US20050206420 Apparatus for latency specific duty cycle correction
09/22/2005DE19706534B4 Halbleitereinrichtung, bei der eine interne Funktion entsprechend einem Potential einer speziellen Anschlußfläche bestimmt wird, und Verfahren des Bestimmens einer internen Funktion einer Halbleitereinrichtung A semiconductor device in which an internal function in accordance with a potential of a specific terminal area is determined, and procedures of determining an internal function of a semiconductor device
09/22/2005DE102005005290A1 Konstantstromquellen-Vorrichtung mit zwei seriellen Verarmungs-MOS-Transistoren Constant current source device with two serial depletion MOS transistors
09/22/2005DE102004032478A1 Verzögerungsregelkreis in Halbleiterspeichervorrichtung und sein Taktsynchronisierverfahren Delay control circuit in semiconductor memory device and its Taktsynchronisierverfahren
09/21/2005EP1456675B1 Input buffer and method for voltage level detection
09/21/2005CN1672328A Method and apparatus for setting the slice level in a binary signal
09/21/2005CN1671043A High-frequency power amplifier and communication apparatus
09/21/2005CN1670688A Universal integrated circuit for balance comparator and linear stepping motor
09/20/2005US6947706 Device for generating a clock signal
09/20/2005US6947510 Circuit for generating an output phase signal with a variable phase shift relative to a reference phase
09/20/2005US6947414 Device for emitting the response of a synchronous system to an asynchronous event
09/20/2005US6946917 Generating an oscillating signal according to a control current
09/20/2005US6946891 Switching circuit device
09/20/2005US6946889 Self alignment system for complement clocks
09/20/2005US6946888 Percent-of-clock delay circuits with enhanced phase jitter immunity
09/20/2005US6946869 Method and structure for short range leakage control in pipelined circuits
09/15/2005WO2005086408A1 Interface device and method for synchronizing data
09/15/2005WO2005085882A1 Frequency sensor and semiconductor device
09/15/2005WO2004100473A3 Signal isolators using micro-transformers
09/15/2005US20050204218 Operation mode setting circuit
09/15/2005US20050201500 Semiconductor integrated circuit and method for testing the same
09/15/2005US20050201457 Distributed arithmetic adaptive filter and method
09/15/2005US20050201455 Equalizer architecture
09/15/2005US20050200396 Power-rail esd clamp circuit for mixed-voltage i/o buffer
09/15/2005US20050200394 Systems and methods for providing distributed control signal redundancy among electronic circuits
09/15/2005US20050200393 Method and device for generating a clock signal with predetermined clock signal properties
09/15/2005US20050200390 Highly configurable PLL architecture for programmable logic
09/15/2005US20050200387 Method for RIAA correction without capacitors in correcting circuits
09/15/2005DE102004009038A1 Verfahren und eine Anordnung zur Reduktion eines dynamischen Offsets bei der Verarbeitung unsymmetrischer Signalfolgen A method and an arrangement for reducing a dynamic offsets in the processing of unbalanced signal sequences
09/14/2005EP1575170A1 Highly configurable pll architecture for programmable logic device
09/14/2005EP1575167A1 Shift resistor and method for driving same
09/14/2005EP1573934A1 Digital filter circuit and method for blocking a transmission line reflection signal
09/14/2005EP1573928A2 Apparatus, and associated method, for performing joint equalization in a multiple-input, multiple-output communication system
09/14/2005EP1573920A2 Low lock time delay locked loops using time cycle suppressor
09/14/2005EP1573912A2 Coarse delay tuner circuits with edge suppressors in delay locked loops
09/14/2005EP0858699B1 Clock signal cleaning circuit
09/14/2005CN2726216Y Pulse conversion regulator
09/14/2005CN2725904Y Clock detector
09/14/2005CN1667957A Highly configurable PLL architecture for programmable logic device
09/14/2005CN1667750A Apparatus for generating internal clock signal
09/13/2005US6944835 Delay circuit, testing apparatus, and capacitor
09/13/2005US6944833 Delay model circuit for use in delay locked loop
09/13/2005US6944804 System and method for measuring pseudo pixel error rate
09/13/2005US6944252 Phase comparator circuit
09/13/2005US6944217 Interleaved finite impulse response filter
09/13/2005US6944089 Synchronous semiconductor device having constant data output time regardless of bit organization, and method of adjusting data output time
09/13/2005US6944070 Integrated circuit devices having high precision digital delay lines therein
09/13/2005US6944040 Programmable delay circuit within a content addressable memory
09/13/2005US6943634 Oscillation detection circuit
09/13/2005US6943619 Practical active capacitor filter
09/13/2005US6943610 Clock distribution network using feedback for skew compensation and jitter filtering
09/13/2005US6943608 Wide frequency range voltage-controlled oscillators (VCO)
09/13/2005US6943607 Method and device for generating delay signal
09/13/2005US6943606 Phase interpolator to interpolate between a plurality of clock phases
09/13/2005US6943604 Device and method for correcting the duty cycle of a clock signal
09/13/2005US6943603 Pulse generating circuit and semiconductor device provided with same
09/13/2005US6943595 Synchronization circuit
09/13/2005US6943591 Apparatus and method for detecting a fault condition in a common-mode signal
09/13/2005US6943590 Clock monitoring apparatus
09/13/2005US6943586 Method and system to temporarily modify an output waveform
09/09/2005WO2005083884A1 Method and system for reducing a dynamic offset during the processing of asymmetric signal strings
09/09/2005WO2005083716A1 Dll circuit
09/09/2005WO2005053159A3 Clock pulse generator apparatus with reduced jitter clock phase
09/08/2005US20050195894 Method and circuit for adaptive equalization of multiple signals in response to a control signal generated from one of the equalized signals
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