Patents
Sitemap › H01 - Basic electric elements › H01L - Semiconductor devices; Electric solid state devices not otherwise provided for › H01L 29 - Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. pn-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
Patents for H01L 29 - Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. pn-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof (218,143)
02/2005
02/15/2005US6855481 Apparatus and a method for forming a pattern using a crystal structure of material
02/15/2005US6855417 Chemical monolayer memory device
02/10/2005WO2005013376A1 Semiconductor magnetic sensor and magnetism measuring instrument using same
02/10/2005WO2005013375A1 Semiconductor device and its manufacturing method
02/10/2005WO2005013374A1 Semiconductor device and method for manufacturing semiconductor device
02/10/2005WO2005013373A1 Eeprom with multi-member floating gate
02/10/2005WO2005013372A2 Spin injection devices
02/10/2005WO2005013371A2 Semiconductor device including band-engineered superlattice
02/10/2005WO2005013361A1 High-heat-resistant semiconductor device
02/10/2005WO2005013350A1 Method of manufacturing a semiconductor device with a bipolar transistor and device with a bipolar transistor
02/10/2005WO2005013349A2 Controlled growth of highly uniform, oxide layers, especially ultrathin layers
02/10/2005WO2005013344A1 Method for slowing down dopand diffusion in semiconductor substrates and devices fabricated therefrom
02/10/2005WO2005013326A2 Epitaxial growth of relaxed silicon germanium layers
02/10/2005WO2005013281A2 Nonvolatile memory and method of making same
02/10/2005WO2004109807A3 Semiconductor structure comprising integrated doping channels
02/10/2005WO2004093439A3 Improved imager light shield
02/10/2005WO2004093197A3 Method for forming structures in finfet devices
02/10/2005WO2004079796A3 Atomic layer deposited dielectric layers
02/10/2005WO2004075370A3 Minimum-dimension, fully-silicided mos driver and esd protection design for optimized inter-finger coupling
02/10/2005WO2004075294A3 Flip-chip component packaging process and flip-chip component
02/10/2005WO2004075151A3 Electrophoretic display with dual-mode switching
02/10/2005WO2004040627A3 Electronic components
02/10/2005US20050033015 Electroluminescent polymers and use thereof in light-emitting devices
02/10/2005US20050032393 Method of composite gate formation
02/10/2005US20050032363 Method for manufacturing a semiconductor device
02/10/2005US20050032361 High aspect ratio contact structure with reduced silicon consumption
02/10/2005US20050032359 Damascene gate process
02/10/2005US20050032345 Group III-nitride growth on Si substrate using oxynitride interlayer
02/10/2005US20050032342 Atomic layer deposition of CMOS gates with variable work functions
02/10/2005US20050032340 Semiconductor device and method of manufacturing the same
02/10/2005US20050032339 Substrate of semiconductor device and fabrication method thereof as well as semiconductor device and fabrication method thereof
02/10/2005US20050032338 Fabricating method of low temperature poly-silicon film and low temperature poly-silicon thin film transistor
02/10/2005US20050032336 Method of manufacturing a semiconductor device
02/10/2005US20050032335 Method to chemically remove metal impurities from polycide gate sidewalls
02/10/2005US20050032334 Semiconductor device and method for manufacturing the same
02/10/2005US20050032327 Fabrication method and device structure of shallow trench insulation for silicon wafer containing silicon-germanium
02/10/2005US20050032323 Flat profile structures for bipolar transistors
02/10/2005US20050032322 Metal oxide semiconductor (MOS) transistors having three dimensional channels and methods of fabricating the same
02/10/2005US20050032321 Strained silicon MOS devices
02/10/2005US20050032320 Method for manufacturing a semiconductor device and a semiconductor device manufactured thereby
02/10/2005US20050032318 Method for making a semiconductor device having a high-k gate dielectric
02/10/2005US20050032317 Methods of forming material on a substrate, and a method of forming a field effect transistor gate oxide on a substrate
02/10/2005US20050032316 Cross diffusion barrier layer in polysilicon
02/10/2005US20050032315 Semiconductor device and method of manufacturing the same
02/10/2005US20050032313 Vertical gain cell
02/10/2005US20050032312 Non-volatile memory device
02/10/2005US20050032311 Fabrication method for memory cell
02/10/2005US20050032310 Semiconductor memory device and manufacturing method thereof
02/10/2005US20050032303 Process for producing an integrated electronic circuit that includes a capacitor
02/10/2005US20050032298 Method of manufacturing a semiconductor integrated circuit device
02/10/2005US20050032297 Field effect transistor fabrication including formation of a channel in a pore
02/10/2005US20050032292 Crystalline or amorphous medium-K gate oxides, Y2O3 and Gd2O3
02/10/2005US20050032291 Methods of forming power semiconductor devices having laterally extending base shielding regions
02/10/2005US20050032287 Semiconductor device and a method of manufacturing the same
02/10/2005US20050032286 Method of manufacturing semiconductor device with triple gate insulating layers
02/10/2005US20050032285 Electronic device and defect repair method thereof
02/10/2005US20050032282 Method of fabricating thin film transistor array
02/10/2005US20050032280 Insulated gate type semiconductor device having a diffusion region contacting bottom and side portions of trenches
02/10/2005US20050032278 Manufacturing method for non-active electrically structures in order to optimize the definition of active electrically structures in an electronic circuit integrated on a semiconductor substrate and corresponding circuit
02/10/2005US20050032276 Semiconductor element and process for manufacturing the same
02/10/2005US20050032275 Mos semiconductor device
02/10/2005US20050032268 Organic thin film transistor and method of manufacturing the same
02/10/2005US20050032263 Method of controlling a capacitance of a thin film transistor liquid crystal display (TFT-LCD) storage capacitor
02/10/2005US20050032260 Method for making an intetgrated circuit comprising a waveguide having an energy band engineered superlattice
02/10/2005US20050032251 Method for manufacturing semiconductor devices by monitoring nitrogen bearing species in gate oxide layer
02/10/2005US20050032247 Method for making an integrated circuit comprising an active optical device having an energy band engineered superlattice
02/10/2005US20050032203 Custom electrodes for molecular memory and logic devices
02/10/2005US20050031836 Pattern forming method, pattern forming apparatus, device manufacturing method, conductive film wiring, electro-optical device, and electronic apparatus
02/10/2005US20050031247 Integrated circuit comprising a waveguide having an energy band engineered superlattice
02/10/2005US20050030825 Structures, methods, and systems for ferroelectric memory transistors
02/10/2005US20050030793 Method for operating a nor-array memory module composed of p-type memory cells
02/10/2005US20050030789 Method for operating a nand-array memory module composed of p-type memory cells
02/10/2005US20050030780 Memory cell
02/10/2005US20050030465 Contact structure of conductive films and thin film transistor array panel including the same
02/10/2005US20050030459 Liquid crystal display and panel therefor
02/10/2005US20050030442 Thin film transistor array substrate for liquid crystal display and method for fabricating the same
02/10/2005US20050030440 Thin film transistor array panel and manufacturing method thereof
02/10/2005US20050030439 Thin film transistor array panel
02/10/2005US20050030107 Semiconductor device
02/10/2005US20050029683 Gettering using voids formed by surface transformation
02/10/2005US20050029682 MOS transistor and fabrication method thereof
02/10/2005US20050029681 Semiconductor memory device and method for producing the same
02/10/2005US20050029678 Growth of single crystal nanowires
02/10/2005US20050029671 Semiconductor device with copper wirings
02/10/2005US20050029654 IC chip with nanowires
02/10/2005US20050029645 Stacked mass storage flash memory package
02/10/2005US20050029628 Semiconductor device whose semiconductor chip has chamfered backside surface edges and method of manufacturing the same
02/10/2005US20050029626 Base for a NPN bipolar transistor
02/10/2005US20050029625 Method and apparatus for allowing formation of self-aligned base contacts
02/10/2005US20050029624 Integrated circuit arrangement having PNP and NPN bipolar transistors, and fabrication method
02/10/2005US20050029623 Semiconductor device
02/10/2005US20050029619 Strained Si/SiGe/SOI islands and processes of making same
02/10/2005US20050029618 Structure and method of forming a dual-trench field effect transistor
02/10/2005US20050029617 Semiconductor module
02/10/2005US20050029616 Semiconductor device and method for manufacturing the same
02/10/2005US20050029615 Schottky barrier diode and manufacturing method thereof
02/10/2005US20050029614 High switching speed two mask schottky diode with high field breakdown
02/10/2005US20050029611 Image sensor comprising thin film transistor optical sensor having offset region and method of manufacturing the same
02/10/2005US20050029605 Highly reliable amorphous high-k gate oxide ZrO2
02/10/2005US20050029604 Atomic layer deposited Zr-Sn-Ti-O films using TiI4
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