| Patents for G06F 13 - Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units (158,002) |
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| 01/04/1995 | EP0632626A1 Method and system for interrupt responsive execution of communications protocols |
| 01/04/1995 | EP0632457A1 Method and system for providing data hold time by synchronous random access memory during write operations |
| 01/04/1995 | EP0632393A1 Hot pluggable motherboard bus connector method |
| 01/04/1995 | EP0632392A1 Semiconductor process, power supply and temperature compensated system bus integrated interface architecture with precision receiver |
| 01/04/1995 | EP0632391A2 Universal asynchronous receiver/transmitter |
| 01/04/1995 | EP0632390A1 Processor circuit comprising a first processor, and system comprising the processor circuit and a second processor |
| 01/04/1995 | EP0632388A1 Processor system particularly for image processing comprising a variable scize memory bus |
| 01/04/1995 | EP0632386A2 System and method for performing improved pseudo-random testing of systems having multi-driver buses |
| 01/04/1995 | EP0632374A2 Method of permitting the exchange of information between processes through a communication device |
| 01/04/1995 | EP0632280A2 Inter-section cross cable detection system |
| 01/04/1995 | EP0631675A1 Use of a language having a similar representation for programmes and data in distributed data processing. |
| 01/04/1995 | EP0440662B1 System bus having multiplexed command/id and data |
| 01/04/1995 | EP0425550B1 Memory control unit |
| 01/04/1995 | CN1097073A Bus structure with second-order parallelism |
| 01/03/1995 | US5379444 Array of one-bit processors each having only one bit of memory |
| 01/03/1995 | US5379437 Reset of peripheral printing devices after a hot plug state |
| 01/03/1995 | US5379434 Apparatus and method for managing interrupts in a multiprocessor system |
| 01/03/1995 | US5379429 Method of resource management for version-up in a computer system and systems therefor |
| 01/03/1995 | US5379421 Interactive terminal for the access of remote database information |
| 01/03/1995 | US5379405 SCSI converter with simple logic circuit arbitration for providing bilateral conversion between single ended signals and differential signals |
| 01/03/1995 | US5379404 Plug code for automatically recognizing and configuring both non-microprocessor and microprocessor based radio frequency communication devices |
| 01/03/1995 | US5379403 Method and interface adapter for interfacing an ISA board to an MCA system by the issuance of an ILLINI-CDCHRDY signal from the interface adapter |
| 01/03/1995 | US5379399 FIFO memory controller for a digital video communications channel having a detector, comparator, and threshold select logic circuit |
| 01/03/1995 | US5379395 Semiconductor integrated circuit for central processor interfacing which enables random and serial access to single port memories |
| 01/03/1995 | US5379389 Method for transmitting commands excluded from a predefined command set |
| 01/03/1995 | US5379386 Micro channel interface controller |
| 01/03/1995 | US5379385 Method and means for effectuating rule based I/O data transfer address control via address control words |
| 01/03/1995 | US5379384 Configuration data loopback in a bus bridge circuit |
| 01/03/1995 | US5379382 Uni and bi-directional signal transfer modes in peripheral controller and method of operating same |
| 01/03/1995 | US5379381 System using separate transfer circuits for performing different transfer operations respectively and scanning I/O devices status upon absence of both operations |
| 01/03/1995 | US5379380 System with dedicated buffers connected to respective I/O devices for continuous processing of digital data |
| 01/03/1995 | US5379379 Memory control unit with selective execution of queued read and write requests |
| 01/03/1995 | US5379378 Data processing system having a bus command generated by one subsystem on behalf of another subsystem |
| 01/03/1995 | US5379374 Collaborative information processing system and workstation |
| 01/03/1995 | US5379307 System for detecting failure in dual bus user network |
| 01/03/1995 | US5379289 For transferring digital data |
| 01/03/1995 | US5378930 Method and arrangement for accomplishing assembly substitution actions during ongoing operation of a bus system |
| 01/03/1995 | US5378067 Network interface apparatus and method for reducing conflicts through the use of times |
| 01/03/1995 | CA2127213A1 Method of permitting the exchange of information between processes through a communication device |
| 01/03/1995 | CA2125339A1 Inter-section cross cable detection system |
| 01/02/1995 | CA2127083A1 Method and system for providing data hold time by synchronous random access memory during write operations |
| 12/31/1994 | CA2125607A1 Method and system for buffering transient data |
| 12/29/1994 | CA2124991A1 System and method for performing improved pseudo-random testing of systems having multi driver buses |
| 12/28/1994 | EP0631413A2 Method for shortest path routing |
| 12/28/1994 | EP0631241A1 Initializing multiple bus networks |
| 12/28/1994 | EP0631240A1 Circuit for data transmission |
| 12/28/1994 | EP0631239A2 Serial data transfer method |
| 12/28/1994 | EP0631238A1 Method and apparatus for pseudo-aligned transfers of data to memory |
| 12/28/1994 | EP0631237A1 Processor circuit comprising a first processor, a memory and a peripheral circuit, and system comprising the processor circuit and a second processor |
| 12/28/1994 | EP0631236A1 A bus-master computer system and method |
| 12/28/1994 | EP0631233A2 Failure recovery for a distributed processing shared resource control |
| 12/28/1994 | EP0630499A1 High-performance non-volatile ram protected write cache accelerator system |
| 12/28/1994 | EP0630496A1 Accelerated token ring network |
| 12/28/1994 | CN1027214C Hub and interface for isochronous token-ring |
| 12/27/1994 | US5377342 Method of controlling a duplex data storage system and data processing system using the same |
| 12/27/1994 | US5377338 Apparatus and methods for reducing numbers of read-modify-write cycles to a memory, and for improving DMA efficiency |
| 12/27/1994 | US5377337 Method and means for enabling virtual addressing control by software users over a hardware page transfer control entity |
| 12/27/1994 | US5377334 Fast asynchronous resource master-slave combination |
| 12/27/1994 | US5377332 Bus arbitration algorithm and apparatus |
| 12/27/1994 | US5377331 Converting a central arbiter to a slave arbiter for interconnected systems |
| 12/27/1994 | US5377328 Technique for providing improved signal integrity on computer systems interface buses |
| 12/27/1994 | US5377325 Bidirectional wait control between host module and slave module |
| 12/27/1994 | US5377322 Information handling method and system utilizing multiple interconnected processors and controllers |
| 12/27/1994 | US5377191 Network communication system |
| 12/27/1994 | US5377184 Method of controlling TWA link in a communications adapter by monitoring buffer fill levels |
| 12/27/1994 | US5377016 Multi-function image processing system |
| 12/27/1994 | US5376928 Exchanging data and clock lines on multiple format data buses |
| 12/27/1994 | CA2027740C Electronic device with data transmission function |
| 12/23/1994 | CA2126297A1 Data communication circuit |
| 12/22/1994 | WO1994029799A1 Cmos bus and transmission line receiver |
| 12/22/1994 | WO1994029798A1 Programmable cmos bus and transmission line driver |
| 12/22/1994 | WO1994029797A1 Multiplex address/data bus with multiplex system controller and method therefor |
| 12/22/1994 | WO1994029791A1 Place object display system |
| 12/22/1994 | WO1994025913A3 Method and apparatus for enterprise desktop management |
| 12/22/1994 | CA2141930A1 Place object display system |
| 12/21/1994 | EP0630141A2 Computer-based multifunction personal communications system |
| 12/21/1994 | EP0630112A2 Transparent latch circuit |
| 12/21/1994 | EP0629961A1 Method and apparatus for conversion of transferred digital data |
| 12/21/1994 | EP0629957A1 Bus system with a reduced number of lines |
| 12/21/1994 | EP0629956A2 Bus-to-bus bridge for optimising data transfers between a system bus and a peripheral bus |
| 12/21/1994 | EP0629955A1 Arbitration logic for multiple bus computer system |
| 12/21/1994 | EP0629954A1 Adapter for transferring blocks of data having a variable length on a system bus |
| 12/21/1994 | EP0629949A2 System and method of recovering from process failure in a write lock control system |
| 12/21/1994 | EP0629947A2 Shared resource control in a distributed processing system |
| 12/21/1994 | EP0629303A1 Apparatus, system and method for facilitating communication between components having different byte orderings |
| 12/20/1994 | US5375236 Down line-loading start control system |
| 12/20/1994 | US5375225 System for emulating I/O device requests through status word locations corresponding to respective device addresses having read/write locations and status information |
| 12/20/1994 | US5375223 Single register arbiter circuit |
| 12/20/1994 | US5375218 DMA channel control apparatus capable of assigning independent DMA transfer control line to respective expansion slots |
| 12/20/1994 | US5375217 Method and apparatus for synchronizing disk drive requests within a disk array |
| 12/20/1994 | US5375215 Multiprocessor system having shared memory divided into a plurality of banks with access queues corresponding to each bank |
| 12/20/1994 | US5375211 Bus error processing system having direct bus master/CPU communication |
| 12/20/1994 | US5375209 Microprocessor for selectively configuring pinout by activating tri-state device to disable internal clock from external pin |
| 12/20/1994 | US5374858 Bus driver circuit |
| 12/14/1994 | EP0629066A1 Checksum arrangement |
| 12/14/1994 | EP0629063A1 Serial bus system |
| 12/14/1994 | EP0628916A1 Microprocessor with multiplexed and non-multiplexed address/data busses |
| 12/14/1994 | EP0628915A1 A two-lined mixed analog/digital bus system and a master station and a slave station for use in such system |
| 12/14/1994 | EP0628914A1 System direct memory access (DMA) support logic for PCI based computer system |
| 12/14/1994 | EP0628913A1 Interrupt signal detection circuit |