Patents
Sitemap › G06 - Computing; Calculating; Counting › G06F - Electric digital data processing › G06F 12 - Accessing, addressing or allocating within memory systems or architectures
Patents for G06F 12 - Accessing, addressing or allocating within memory systems or architectures (152,539)
04/1989
04/12/1989EP0311034A2 Cache memory control apparatus for a virtual memory data-processing system
04/11/1989US4821254 Information recording and reproducing apparatus which detects deterioration of a medium in each sector before recording
04/11/1989US4821172 Apparatus for controlling data transfer between storages
04/11/1989US4821171 System of selective purging of address translation in computer memories
04/11/1989US4821169 Access verification arrangement for digital data processing system which has demand-paged memory with page crossing detection
04/11/1989CA1252575A1 Bus control gate array
04/11/1989CA1252573A1 Dual bus system
04/11/1989CA1252572A1 Computer with virtual machine mode and multiple protection rings
04/11/1989CA1252537A1 Data transmission system
04/06/1989WO1989003089A2 Cache/disk system having command selection based on disk access time
04/06/1989WO1989003082A1 Method of storing data
04/06/1989WO1989003081A1 Device for protecting memory areas of an electronic microprocessor system
04/05/1989EP0310496A2 Synchronous semiconductor memory device
04/05/1989EP0310446A2 Cache memory management method
04/05/1989EP0310444A2 Multi-mode control of virtually-addressed unified cache
04/05/1989EP0309995A2 System for fast selection of non-cacheable address ranges using programmed array logic
04/05/1989EP0309994A2 Method and apparatus for implementing memory coherency
04/05/1989EP0309798A2 System and method of building and searching a new data base table
04/05/1989EP0309793A2 Method and apparatus for testing an integrated circuit including a microprocessor and an instruction cache
04/05/1989EP0309737A2 System for creating an LRU-like mechanism for more than three terms by binary matrix trees
04/05/1989EP0309712A2 System for creating an LRU-like mechanism for more than three terms by binary matrix trees
04/05/1989EP0309668A2 Circuit for implementing a LRU(Least Recently Used)-like mechanism for a lot of elements, in particular for data processing systems
04/05/1989EP0309667A2 Layout for data processing systems implementing a modulary organised expandable LRU(Least Recently Used)-like mechanism for n elements
04/05/1989EP0160028B1 Device and process for a fast and stable storage of data
04/05/1989EP0044628B1 Redundancy scheme for an mos memory
04/04/1989US4819211 Microcomputer system for high speed address translation
04/04/1989US4819204 Method for controlling memory access on a chip card and apparatus for carrying out the method
04/04/1989US4819203 Control system for interruption long data transfers between a disk unit or disk coche and main memory to execute input/output instructions
04/04/1989US4819160 Method of processing data access in a database management system with data dictionary directory
04/04/1989US4819158 Microprocessor with an interruptable bus cycle
04/04/1989US4819156 Database index journaling for enhanced recovery
04/04/1989US4819154 Memory back up system with one cache memory and two physically separated main memories
04/04/1989US4819152 Method and apparatus for addressing a memory by array transformations
04/04/1989US4818932 Digital oscilloscope
03/1989
03/30/1989DE3831530A1 Data processing circuit to process data with different bit lengths
03/30/1989DE3731339A1 Method of monitoring memory devices in digitally controlled communication systems
03/29/1989EP0309068A2 Digital data processing system
03/28/1989US4817140 Software protection system using a single-key cryptosystem, a hardware-based authorization system and a secure coprocessor
03/28/1989US4817095 Byte write error code method and apparatus
03/28/1989US4817091 Fault-tolerant multiprocessor system
03/28/1989US4816997 Bus master having selective burst deferral
03/28/1989US4816991 Virtual machine system with address translation buffer for holding host and plural guest entries
03/28/1989US4816653 Security file system for a portable data carrier
03/22/1989EP0308219A2 Microcomputer with internal RAM security during external program mode
03/22/1989EP0308183A2 Information recording medium
03/22/1989EP0307945A2 Memory control apparatus for use in a data processing system
03/22/1989EP0307649A2 Data processing system for utilizing a memory-mapped coprocessor within a limited address space
03/21/1989US4815039 Fast real-time arbiter
03/21/1989US4815034 Dynamic memory address system for I/O devices
03/21/1989US4815032 Portable electronic memorandum device with password accessible memory
03/21/1989US4815030 Multitask subscription data retrieval system
03/21/1989US4815028 Data recovery system capable of performing transaction processing in parallel with data recovery processing
03/21/1989US4815010 Virtual memory image controller for multi-windowing
03/21/1989US4815005 Semantic network machine for artificial intelligence computer
03/21/1989US4814982 Reconfigurable, multiprocessor system with protected, multiple, memories
03/21/1989US4814981 Cache invalidate protocol for digital data processing system
03/21/1989US4814977 Apparatus and method for direct memory to peripheral and peripheral to memory data transfers
03/21/1989US4814976 RISC computer with unaligned reference handling and method for the same
03/21/1989US4814975 Virtual machine system and method for controlling machines of different architectures
03/21/1989US4814749 Protection system
03/21/1989US4813912 For securing operation against tampering
03/21/1989CA1251568A1 Image signal processor
03/15/1989EP0306994A2 Semiconductor memory device with an improved serial addressing structure
03/15/1989EP0306953A2 Address/control signal input circuit for cache controller
03/15/1989EP0167540B1 Processing system tolerant of loss of access to secondary storage
03/15/1989EP0150195B1 Demand paging scheme for a multi-atb shared memory processing system
03/15/1989EP0097159B1 Two bit per symbol sec/ded code
03/14/1989US4813024 Integrated circuit for the confidential storage and processing of data, comprising a device against fraudulent use
03/14/1989US4813002 High speed high density dynamic address translator
03/14/1989US4812981 Memory management system improving the efficiency of fork operations
03/14/1989US4812969 Address translation unit
03/14/1989US4812675 Security element circuit for programmable logic array
03/14/1989US4812198 Transporter-presser also removes protective film from adhesive
03/14/1989CA1251284A1 Dual operating mode microprocessor having a re-mapper unit
03/09/1989WO1989002122A1 Arrangement and process for detecting and localizing faulty circuits in a storage component
03/08/1989EP0306395A1 Light detection circuit
03/08/1989EP0306357A1 Memory access management unit with logical unvarying identifiers, especially for data base management
03/08/1989EP0306197A2 A method for computing transitive closure
03/08/1989EP0097234B1 Method and apparatus for restarting a computing system
03/07/1989US4811411 Image processing method and system
03/07/1989US4811347 Apparatus and method for monitoring memory accesses and detecting memory errors
03/07/1989US4811297 Boundary-free semiconductor memory device
03/07/1989US4811294 Data integrity verifying circuit for electrically erasable and programmable read only memory (EEPROM)
03/07/1989US4811293 Method for storing data in an electrically erasable memory for carrying out this method
03/07/1989US4811291 Safety device for electrically programmable read-only memory
03/07/1989US4811288 Data security device for protecting stored data
03/07/1989US4811280 Dual mode disk controller
03/07/1989US4811216 Multiprocessor memory management method
03/07/1989US4811215 Instruction execution accelerator for a pipelined digital machine with virtual memory
03/07/1989US4811212 Address transformation circuit arrangement
03/07/1989US4811209 Cache memory with multiple valid bits for each data indication the validity within different contents
03/07/1989US4811208 Stack frame cache on a microprocessor chip
03/07/1989US4811207 Join operation processing system in distributed data base management system
03/07/1989US4811206 Data processing system with overlapped address translation and address computation
03/07/1989US4811203 Hierarchial memory system with separate criteria for replacement and writeback without replacement
03/07/1989US4811202 Quadruply extended time multiplexed information bus for reducing the `pin out` configuration of a semiconductor chip package
03/01/1989EP0304806A2 System for data and address management in a cache coupled between a central processor and a main memory
03/01/1989EP0304615A2 Data rearrangement processor
03/01/1989EP0304587A2 Interruptible cache loading
03/01/1989EP0304540A2 A method of initializing a data processing system
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