Patents
Sitemap › G06 - Computing; Calculating; Counting › G06F - Electric digital data processing › G06F 12 - Accessing, addressing or allocating within memory systems or architectures
Patents for G06F 12 - Accessing, addressing or allocating within memory systems or architectures (152,539)
08/1990
08/29/1990EP0384102A2 Multi-processor caches with large granularity exclusivity locking
08/29/1990EP0383891A1 Pipelined address check bit stack controller.
08/29/1990EP0383850A1 Method of integrating software application programs using an attributive data model database
08/28/1990US4953164 Cache memory system having error correcting circuit
08/28/1990US4953132 Memory circuit for and method of protecting memory data integrity during an output operation utilizing memory data
08/28/1990US4953101 Software configurable memory architecture for data processing system having graphics capability
08/28/1990US4953080 Object management facility for maintaining data in a computer system
08/28/1990US4953079 Cache memory address modifier for dynamic alteration of cache block fetch sequence
08/28/1990US4953077 Data processing system
08/28/1990US4953073 Cup chip having tag comparator and address translation unit on chip and connected to off-chip cache and main memories
08/28/1990US4952796 Light detection circuit having a junction reverse-biased by a current generator
08/28/1990CA1273436A1 Network interface module with minimized data paths
08/28/1990CA1273435A1 Method and means for loading and storing data in a reduced instruction set computer
08/28/1990CA1273434A1 Method for restarting a long-running, fault-tolerant operation in a transaction-oriented data base system without burdening the system log
08/23/1990DE4005319A1 Maintaining data consistency in multiprocessor system - controlling working memory via buffer memory to store data to be transmitted in intermediate stage
08/22/1990EP0383097A2 Cache memory
08/22/1990EP0382910A2 Virtual address translation
08/21/1990US4951248 Self configuring memory system
08/21/1990US4951247 Data exchange system comprising a plurality of user terminals each containing a chip card reading device
08/21/1990US4951246 Nibble-mode dram solid state storage device
08/21/1990US4951194 Method for reducing memory allocations and data copying operations during program calling sequences
08/21/1990CA2005699A1 Memory block address determination circuit
08/21/1990CA1273126A1 Instruction for implementing a secure computer system
08/21/1990CA1273125A1 Memory management system
08/21/1990CA1273124A1 Ram memory overlay gate array circuit
08/21/1990CA1273123A1 Vector access control system
08/21/1990CA1273116A1 Method of distributed file recovery and a system using the method
08/21/1990CA1273109A1 Secured printer for a value printing system
08/16/1990EP0382529A2 Microprocessor having store buffer
08/16/1990EP0382396A2 Program memory buffer for processor
08/16/1990EP0382390A2 Method and means for error checking of dram-control signals between system modules
08/16/1990EP0382358A2 Full address and odd boundary direct memory access controller
08/16/1990EP0382246A2 Bit addressing system
08/16/1990EP0382237A2 Multiprocessing system having a single translation lookaside buffer with reduced processor overhead
08/16/1990EP0381885A2 Method for identifying bad data
08/16/1990DE4001165A1 Anweisungseinrichtung und verfahren zum pipeline-laden von daten in einen prozessor Instruction means and methods for pipelined loading of data into a processor
08/15/1990CN1009227B Computer system
08/14/1990US4949301 Improved pointer FIFO controller for converting a standard RAM into a simulated dual FIFO by controlling the RAM's address inputs
08/14/1990US4949298 Memory cartridge having a multi-memory controller with memory bank switching capabilities and data processing apparatus
08/14/1990US4949251 Exactly-once semantics in a TP queuing system
08/14/1990US4949244 Storage system
08/14/1990US4949239 System for implementing multiple lock indicators on synchronous pended bus in multiprocessor computer system
08/14/1990US4949238 Apparatus for detecting memory protection violation
08/14/1990CA1272807A1 Peripheral bus
08/08/1990EP0381651A2 Managing method and apparatus for data storage
08/08/1990EP0381644A2 Multi-processor system and method for maintaining the reliability of shared data structures
08/08/1990EP0381470A2 Processing of memory access exceptions along with prefetched instructions within the instruction pipeline of a virtual memory system-based digital computer
08/08/1990EP0381447A2 Method and apparatus for controlling the conversion of virtual to physical memory addresses in a digital computer system
08/08/1990EP0381325A2 Synchronising and processing of memory access operations
08/08/1990EP0381323A2 Method and apparatus for increasing the data storage rate of a computer system
08/08/1990EP0381245A2 Address translation system
08/08/1990EP0381167A2 Method for managing multiple virtual storages divided into families
08/08/1990EP0381140A2 Data processing apparatus
08/08/1990EP0381064A2 Addressing mechanism for accessing multiple neighboring locations from full field memory in parallel
08/08/1990EP0381059A2 Arithmetic element controller
08/08/1990EP0380966A1 Information management system, particularly for use in picture archive and communications systems
08/08/1990EP0380861A2 Improved data consistency between cache memories and the main memory in a multi-processor computer system
08/08/1990EP0380855A2 Memory configuration for use with means for interfacing a system control unit for a multi-processor system with the system main memory
08/08/1990EP0380853A2 Write back buffer with error correcting capabilities
08/08/1990EP0380844A2 Method and means for interfacing a system control unit for a multi-processor system with the system main memory
08/08/1990EP0380842A2 Method and apparatus for interfacing a system control unit for a multiprocessor system with the central processing units
08/07/1990US4947477 Partitionable embedded program and data memory for a central processing unit
08/07/1990US4947396 Method and system for detecting data error
08/07/1990US4947393 Activity verification system for memory or logic
08/07/1990US4947370 Word processor for simultaneously displaying and scrolling documents and the corresponding titles
08/07/1990US4947342 Graphic processing system for displaying characters and pictures at high speed
08/07/1990US4947320 Method for referential constraint enforcement in a database management system
08/07/1990US4947319 Arbitral dynamic cache using processor storage
08/07/1990US4947318 Data processing security system for automatically transferring software protection data from removable store into internal memory upon mounting of stores
08/07/1990US4947162 Terminal device for a monitoring and control system
08/07/1990CA2007443A1 Full address and odd boundary direct memory access controller
08/07/1990CA1272523A1 Universal module interface
08/02/1990DE3901457A1 Verfahren zur adressbereichsueberwachung bei datenverarbeitungsgeraeten in echtzeit Method for adressbereichsueberwachung at computers in real time
08/02/1990CA2008868A1 Initiazation of a main storage
08/01/1990EP0380240A2 Coded signature indexed databases
08/01/1990EP0380093A2 Data transfer controller using dummy signals for continued operation under insignificant faulty conditions
08/01/1990EP0379778A2 Virtual memory management arrangement for addressing multi-dimensional arrays in a digital data processing system and method therefor
08/01/1990EP0379772A2 Programmable data transfer timing
08/01/1990EP0379771A2 Read Abort Process
08/01/1990EP0379770A2 Address transfer error detection process
08/01/1990EP0379769A2 Write-read/write-pass memory subsystem cycle
08/01/1990EP0379768A2 Read-modify-write operation
07/1990
07/31/1990US4945512 High-speed partitioned set associative cache memory
07/31/1990US4945480 Data domain switching on program address space switching and return
07/31/1990US4945476 Interactive system and method for creating and editing a knowledge base for use as a computerized aid to the cognitive process of diagnosis
07/31/1990US4945474 Method for restoring a database after I/O error employing write-ahead logging protocols
07/31/1990US4945472 Data processor with I/O area detection
07/31/1990US4945469 High speed stack circuit for register data in a microcomputer
07/31/1990CA1272312A1 Method and system for processing a two-dimensional image in a microprocessor
07/31/1990CA1272301A1 Cache-memory management unit system
07/31/1990CA1272261A1 Addressing for a multipoint communication system for patient monitoring
07/25/1990EP0379316A2 Request cancel system
07/25/1990EP0379178A2 Computer memory controller power saving management
07/25/1990EP0378538A1 Arrangement and process for detecting and localizing faulty circuits in a storage component.
07/24/1990US4943966 For allocating memory address base addresses among memory units
07/24/1990US4943961 Memory retention system for volatile memory devices
07/24/1990US4943947 Semiconductor memory device with an improved serial addressing structure
07/24/1990US4943946 Control system for chained circuit modules
07/24/1990US4943937 Apparatus for processing images having desired gray levels including a three-dimensional frame memory
07/24/1990US4943914 Storage control system in which real address portion of TLB is on same chip as BAA
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