Patents for G06F 12 - Accessing, addressing or allocating within memory systems or architectures (152,539) |
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05/18/1988 | EP0267379A2 Data base access mechanism for rules utilized by a synthesis procedure for logic circuit design |
05/18/1988 | EP0267259A1 Security file system for a portable data carrier. |
05/18/1988 | EP0157075B1 Modular data processing system |
05/17/1988 | US4745407 Memory organization apparatus and method |
05/17/1988 | CA1236924A2 Memory system for sequential storage and retrieval of video data |
05/11/1988 | EP0267114A1 Integrated circuit for memorizing and confidentially processing information, comprising an anti-fraud device |
05/11/1988 | EP0266784A2 Database access machine for factory automation |
05/11/1988 | EP0266505A2 Versioning of message formats in a 24-hour operating environment |
05/11/1988 | EP0266431A1 Image processor |
05/11/1988 | EP0266428A1 Method of assigning a board slot number |
05/11/1988 | EP0266371A1 Specialized parity detection system for wide memory structure |
05/10/1988 | US4744061 Dynamic semiconductor memory device having a simultaneous test function for divided memory cell blocks |
05/10/1988 | US4744049 Microcode testing of a cache in a data processor |
05/10/1988 | US4744043 Data processor execution unit which receives data with reduced instruction overhead |
05/10/1988 | US4744025 Arrangement for expanding memory capacity |
05/10/1988 | EP0166739A4 Semiconductor memory device for serial scan applications. |
05/10/1988 | CA1236599A1 Dual purpose screen/memory refresh counter |
05/10/1988 | CA1236589A1 Apparatus for masking the contents of a first storage means from a system until the contents of a second storage means is executed by said system |
05/10/1988 | CA1236588A1 Dynamically allocated local/global storage system |
05/05/1988 | DE3736455A1 Hierarchisches ablagesystem Hierarchical system tray |
05/04/1988 | EP0266016A2 Automatic circuit board configuration |
05/04/1988 | EP0265948A2 Data processor capable of immediately calculating branch address in relative address branch |
05/04/1988 | EP0265905A2 Addressing device for modules |
05/04/1988 | EP0265636A1 Multiprocessor with several processors provided with cache memories and a shared memory |
05/04/1988 | EP0265575A1 Data processing system having automatic address allocation arrangements for addressing interface cards |
05/03/1988 | US4742474 Variable access frame buffer memory |
05/03/1988 | US4742469 Electronic meter circuitry |
05/03/1988 | US4742454 Apparatus for buffer control bypass |
05/03/1988 | US4742450 Method for facilitating the interchange of data stored in a Unix file |
05/03/1988 | US4742447 Method to control I/O accesses in a multi-tasking virtual memory virtual machine type data processing system |
05/03/1988 | US4742446 Computer system using cache buffer storage unit and independent storage buffer device for store through operation |
04/27/1988 | EP0265312A1 Integrated circuit of the logic type comprising an EEPROM |
04/27/1988 | EP0265183A2 Billing system for computer software |
04/27/1988 | EP0265108A2 Cache storage priority |
04/27/1988 | EP0264912A2 Storage control system and logic-in memory device therefor |
04/26/1988 | US4740971 Tag buffer with testing capability |
04/26/1988 | US4740938 Apparatus for rapid reproduction of information from a record carrier |
04/26/1988 | US4740927 Bit addressable multidimensional array |
04/26/1988 | US4740916 Reconfigurable contiguous address space memory system including serially connected variable capacity memory modules and a split address bus |
04/26/1988 | US4740911 Data processing system |
04/26/1988 | US4740895 Method of testing equipment |
04/26/1988 | US4740889 Cache disable for a data processor |
04/26/1988 | CA1235821A1 Data processor having module access control |
04/26/1988 | CA1235816A1 Error recovery system in a data processor having a control storage |
04/21/1988 | DE3633227A1 Arrangement for conversion of a virtual address into a physical address for a working memory organised in pages in a data processing system |
04/20/1988 | EP0263924A2 On-chip bit reordering structure |
04/19/1988 | US4739473 Computer memory apparatus |
04/19/1988 | US4739471 Method and means for moving bytes in a reduced instruction set computer |
04/12/1988 | US4737931 Memory control device |
04/12/1988 | US4737909 Cache memory address apparatus |
04/12/1988 | US4737908 Buffer memory control system |
04/12/1988 | CA1235231A1 I/o controller for multiple disparate serial memories with a cache |
04/06/1988 | EP0263014A1 Method for file management on a read-only information carrier |
04/06/1988 | EP0262750A2 Very large scale parallel computer |
04/06/1988 | EP0262486A1 Address management unit of a central multiprocessor control unit of a telecommunication exchange system |
04/06/1988 | EP0262477A2 Circuit arrangement for the transmission of data signals |
04/06/1988 | EP0262452A2 Redundant storage device having address determined by parity of lower address bits |
04/06/1988 | EP0262301A2 Paging supervisor |
04/06/1988 | CN87106651A 计算机系统 Computer Systems |
04/05/1988 | US4736293 Interleaved set-associative memory |
04/05/1988 | US4736290 Microprocessors |
04/05/1988 | US4736287 Set association memory system |
04/05/1988 | CA1234920A1 Rom protection scheme |
03/31/1988 | DE3728496A1 Image processing memory device |
03/30/1988 | EP0262025A2 System for permitting access to data field area in IC card for multiple services |
03/30/1988 | EP0261947A1 Computer system |
03/30/1988 | EP0261751A2 Concurrent memory access system |
03/30/1988 | EP0261497A2 Semaphore circuit for shared memory cells |
03/30/1988 | EP0261162A1 Method for qualitative saving of digitized data. |
03/30/1988 | EP0046781B1 Cached multiprocessor system with pipeline timing |
03/29/1988 | US4734884 Magnetic bubble memory system with function of protecting specific storage area of bubble memory from rewriting |
03/29/1988 | US4734855 Apparatus and method for fast and stable data storage |
03/29/1988 | US4734851 Write protect control circuit for computer hard disc systems |
03/29/1988 | US4734850 Data process system including plural storage means each capable of concurrent and intermediate reading and writing of a set of data signals |
03/29/1988 | CA1234639A1 Ports zone control |
03/29/1988 | CA1234633A1 Compression of data for storage |
03/24/1988 | WO1988002148A1 A transparent translation method and apparatus for use in a memory management unit |
03/23/1988 | EP0261031A2 Method and apparatus for error correction in a parallel processor data processing system |
03/23/1988 | EP0261030A2 System for data field area acquisition in IC card for multiple services |
03/23/1988 | EP0261029A2 Cache invalidate protocol for digital data processing system |
03/23/1988 | EP0260862A2 Move-out queue buffer |
03/23/1988 | EP0260837A2 Microprocessor with selective cache memory |
03/23/1988 | EP0260458A2 Networking processors |
03/23/1988 | EP0260433A2 Multi-address space control method |
03/22/1988 | US4733386 Method of writing file data into a write-once type memory device |
03/22/1988 | US4733367 Swap control apparatus for hierarchical memory system |
03/22/1988 | US4733352 Lock control for a shared storage in a data processing system |
03/22/1988 | US4733350 Improved purge arrangement for an address translation control system |
03/22/1988 | US4733349 Method for recording and managing processing history information using a plurality of storage devices |
03/22/1988 | US4733348 Virtual-memory multiprocessor system for parallel purge operation |
03/22/1988 | US4733344 Data processing apparatus for controlling reading out of operands from two buffer storages |
03/22/1988 | US4733265 Data retaining apparatus for a camera |
03/16/1988 | EP0259967A2 Directory memory |
03/16/1988 | EP0259912A1 File backup facility for a community of personal computers |
03/16/1988 | EP0259859A2 Information processing system capable of reducing invalid memory operations by detecting an error in a main memory |
03/16/1988 | EP0034188B1 Error correction system |
03/15/1988 | US4731758 Dual array memory with inter-array bi-directional data transfer |
03/15/1988 | US4731749 Electronic postage meter having multiple non-volatile memories for storing different historical information reflecting postage transactions |
03/15/1988 | US4731748 Pocket computer with means for checking the detachable memory module before and after power interruption |
03/15/1988 | US4731740 Translation lookaside buffer control system in computer or virtual memory control scheme |