| Patents for G06F 12 - Accessing, addressing or allocating within memory systems or architectures (152,539) |
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| 03/15/1988 | US4731739 Eviction control apparatus |
| 03/15/1988 | US4731738 For use in a processing unit |
| 03/15/1988 | US4731737 High speed intelligent distributed control memory system |
| 03/15/1988 | US4731724 System for simultaneous transmission of data blocks or vectors between a memory and one or a number of data-processing units |
| 03/15/1988 | US4731664 Method and arrangement for refreshing a frame memory in an interframe encoding system |
| 03/15/1988 | CA1234224A1 Computer memory management system |
| 03/10/1988 | WO1988001772A1 A system to allocate the resources of a very large scale computer |
| 03/09/1988 | EP0259095A2 Cache storage queue |
| 03/09/1988 | EP0259053A2 Variable data compression announcement circuit |
| 03/09/1988 | EP0259050A2 Multi-channel memory access circuit |
| 03/09/1988 | EP0258867A2 Multitask subscription data retrieval method |
| 03/09/1988 | EP0258559A2 Cache memory coherency control provided with a read in progress indicating memory |
| 03/09/1988 | CN87106067A Very large scale computer |
| 03/08/1988 | US4730261 Solids modelling generator |
| 03/08/1988 | US4730252 For use in a word processing system |
| 03/08/1988 | US4730251 Automatic I/O address assignment |
| 03/08/1988 | US4730249 Method to operate on large segments of data in a virtual memory data processing system |
| 03/08/1988 | CA1233909A1 External interface control circuitry for microcomputer systems |
| 03/08/1988 | CA1233908A2 Multilevel controller for a cache memory interface in a multiprocessing system |
| 03/03/1988 | DE3629399A1 Method for operating the central memory of a multiprocessor-type common control unit of a switching system |
| 03/02/1988 | EP0258104A1 Method of determining and of modifying a partition in a memory space of a non-erasable carrier |
| 03/02/1988 | EP0257938A2 Digital memory with reset/preset capabilities |
| 03/02/1988 | EP0257405A1 Method and apparatus for updating control bit combinations |
| 03/02/1988 | EP0257061A1 Multi-processor apparatus |
| 03/02/1988 | EP0056400B1 Memory security circuit |
| 03/01/1988 | US4729092 Two store data storage apparatus having a prefetch system for the second store |
| 03/01/1988 | US4729091 Directing storage requests prior to address comparator initialization with a reference address range |
| 02/25/1988 | WO1988001411A1 A content-addressable memory system |
| 02/25/1988 | WO1988001408A1 System for controlling access to a store of information |
| 02/24/1988 | EP0256881A2 An automated method for creating a configuration database |
| 02/24/1988 | EP0256864A2 Digital data processing apparatus |
| 02/24/1988 | EP0042000B1 Cache memory in which the data block size is variable |
| 02/23/1988 | US4727510 System for addressing a multibank memory system |
| 02/23/1988 | US4727491 Personal computer having normal and high speed execution modes |
| 02/23/1988 | US4727486 Hardware demand fetch cycle system interface |
| 02/23/1988 | US4727485 Paged memory management unit which locks translators in translation cache if lock specified in translation table |
| 02/23/1988 | US4727484 Memory address control apparatus with separate translation look aside buffers for a data processor using a virtual memory technique |
| 02/23/1988 | US4727482 Apparatus for enhancing searches of data tables |
| 02/23/1988 | US4727475 Self-configuring modular computer system with automatic address initialization |
| 02/23/1988 | US4727474 Staging memory for massively parallel processor |
| 02/23/1988 | CA1233273A2 Method for controlling buffer memory in data processing apparatus |
| 02/23/1988 | CA1233272A1 Distributed cache in dynamic rams |
| 02/23/1988 | CA1233271A1 Cache disable for a data processor |
| 02/23/1988 | CA1233269A1 Data structure for a document processing system |
| 02/23/1988 | CA1233264A1 Data processor having dynamic bus sizing |
| 02/23/1988 | CA1233259A1 High performance memory utilizing pipelining techniques |
| 02/17/1988 | CN87104487A Apparatus and method for page frame replacement in data processing sgstem having virtual memory addressing |
| 02/16/1988 | US4725945 Distributed cache in dynamic rams |
| 02/16/1988 | CA1232970A1 Data processing system provided with a memory access controller |
| 02/16/1988 | CA1232969A1 Personal computer having normal and high speed execution modes |
| 02/10/1988 | CN87105300A Cache directory and control |
| 02/09/1988 | US4724531 Gate array with bidirectional symmetry |
| 02/09/1988 | US4724519 Channel number priority assignment apparatus |
| 02/09/1988 | US4724518 Odd/even storage in cache memory |
| 02/09/1988 | CA1232677A1 Data processing system with reorganization of disk storage for improved paging |
| 02/03/1988 | EP0255414A1 Integrated protection circuit with a memory having two selectable address areas |
| 02/03/1988 | EP0255186A2 System and method for parallel processing with mostly functional languages |
| 02/03/1988 | EP0254854A2 Multiple CPU program management |
| 02/02/1988 | US4723223 Direct memory access controller for reducing access time to transfer information from a disk |
| 02/02/1988 | CA1232355A1 Single in-line memory module |
| 01/27/1988 | EP0254602A2 Read only memory |
| 01/27/1988 | EP0254270A2 High speed high density dynamic address translator |
| 01/27/1988 | EP0254247A2 Calculator status saving system |
| 01/27/1988 | EP0253956A2 An addressing technique for providing simultaneous read modify and write operations with serpentine configured rams |
| 01/27/1988 | EP0253824A1 Paged memory management unit capable of selectively supporting multiple address spaces. |
| 01/26/1988 | US4722050 Method and apparatus for facilitating instruction processing of a digital computer |
| 01/26/1988 | US4722047 Prefetch circuit and associated method for operation with a virtual command emulator |
| 01/26/1988 | US4722046 Data processing apparatus |
| 01/26/1988 | CA1232078A1 Computer interface |
| 01/21/1988 | DE3628259C1 Method and arrangement for control of access to the memory system consisting of cache memory and working memory in a data processing system |
| 01/20/1988 | EP0253095A2 Memory interface system |
| 01/14/1988 | WO1988000372A1 One-time programmable data security system for programmable logic device |
| 01/12/1988 | US4719570 Apparatus for prefetching instructions |
| 01/12/1988 | US4719568 Hierarchical memory system including separate cache memories for storing data and instructions |
| 01/12/1988 | CA1231463A1 Memory access control apparatus |
| 01/12/1988 | CA1231462A1 Apparatus and method for high-speed, stable storage of information |
| 01/12/1988 | CA1231460A1 Real time data transformation and transmission overlapping device |
| 01/12/1988 | CA1231456A1 Extended error correction for package error correction codes |
| 01/07/1988 | EP0252042A1 Method and apparatus for determining in a computer which of a number of programmes are allowed to utilise a rapid access memory |
| 01/07/1988 | EP0251861A1 Memory management unit |
| 01/07/1988 | EP0251853A1 Integrated circuit for memorizing and confidentially processing information, comprising an anti-fraud device |
| 01/07/1988 | EP0251594A2 Database system for parallel processor |
| 01/07/1988 | EP0251461A2 Parallel free storage management method and device |
| 01/07/1988 | EP0251056A2 Cache tag lookaside |
| 01/07/1988 | EP0250952A2 Microcomputer |
| 01/07/1988 | EP0250876A2 Apparatus and method for page replacement in a data-processing system having a virtual memory |
| 01/07/1988 | EP0250847A2 Managing log data in a transaction-oriented system |
| 01/07/1988 | EP0250702A2 Cache memory with variable fetch and replacement schemes |
| 01/06/1988 | CN87104515A Arragements for programme control |
| 01/05/1988 | US4718044 Electronic apparatus having plural detachable memories |
| 01/05/1988 | US4718039 Intermediate memory array with a parallel port and a buffered serial port |
| 01/05/1988 | US4718038 Data security device for storing data at a peripheral part of the device during power down thus preventing improper retrieval |
| 01/05/1988 | US4718008 Method to control paging subsystem processing in a virtual memory data processing system during execution of critical code sections |
| 01/05/1988 | CA1231178A1 Access-arbitration scheme |
| 01/05/1988 | CA1231166A1 Bus networks for digital data processing systems and modules usable therewith |
| 12/30/1987 | CN87101605A Apparatus and method for addressing semiconductor arrays in main memory unit on consecutive system clock cycles |
| 12/29/1987 | US4716566 Error correcting system |
| 12/29/1987 | US4716545 Memory means with multiple word read and single word write |
| 12/29/1987 | US4716533 Image translation system |
| 12/29/1987 | US4716528 Method for managing lock escalation in a multiprocessing, multiprogramming environment |