Patents for G06F 12 - Accessing, addressing or allocating within memory systems or architectures (152,539) |
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10/20/1987 | US4701844 Dual cache for independent prefetch and execution units |
10/20/1987 | US4701840 Secure data processing system architecture |
10/20/1987 | CA1228437A1 Image processing system |
10/14/1987 | EP0241129A2 Addressing arrangement for a RAM buffer controller |
10/14/1987 | EP0241124A2 Single/dual access storage device |
10/14/1987 | EP0241078A1 Memory comprising simultaneously addressable memory elements |
10/14/1987 | EP0240616A1 Method to test and set data in a record on disk in one atomic input/output operation |
10/14/1987 | CN87102475A Control system for shared storage of multiprocessor system consisted of many processor systems |
10/13/1987 | US4700291 Memory address control apparatus with separate translation look aside buffers for a data processor using a virtual memory technique |
10/13/1987 | CA1228171A1 Working set prefetch for level two caches |
10/13/1987 | CA1228170A1 Architecture for small instruction caches |
10/13/1987 | CA1228169A1 Self-archiving data recording |
10/08/1987 | WO1987006049A1 System for writing rom cassette for a programmable machine controller |
10/07/1987 | EP0239951A2 Pseudo-static memory subsystem |
10/07/1987 | EP0239827A2 Method for the control of a common memory of a multiprocessor system comprising separate microprocessor systems |
10/07/1987 | EP0239715A2 Management of the size and number of memory segments allocated to processes in a multiprocessing environment |
10/06/1987 | US4698808 Method for detecting intermittent error in volatile memory |
10/06/1987 | US4698750 Security for integrated circuit microcomputer with EEPROM |
10/06/1987 | US4698749 RAM memory overlay gate array circuit |
10/06/1987 | US4698617 ROM Protection scheme |
10/06/1987 | CA1227885A1 Secure data processing system architecture |
09/30/1987 | EP0239359A2 Address translation circuit |
09/30/1987 | EP0239299A2 Overlapped control store |
09/30/1987 | EP0239283A2 Microcomputer |
09/30/1987 | EP0239269A2 Image processing method and system |
09/30/1987 | EP0239224A2 Random access memory apparatus |
09/30/1987 | EP0239181A2 Interrupt requests serializing in a virtual memory data processing system |
09/30/1987 | EP0239119A2 Information transferring method and apparatus of transferring information from one memory area to another memory area |
09/30/1987 | EP0238810A2 Method and system for facilitating instruction processing of a digital computer |
09/30/1987 | EP0238550A1 Memory system with page mode operation. |
09/30/1987 | EP0238537A1 System for preventing software piracy employing multi-encrypted keys and single decryption circuit modules. |
09/30/1987 | EP0032956B1 Data processing system utilizing hierarchical memory |
09/29/1987 | US4697266 Asynchronous checkpointing system for error recovery |
09/24/1987 | WO1987005726A1 Method and device for qualitative saving of digitized data |
09/24/1987 | WO1987005724A2 Random address system for circuit modules |
09/23/1987 | EP0238158A2 Copy-on-write segment sharing in a virtual memory, virtual machine data processing system |
09/23/1987 | EP0238090A2 Microcomputer capable of accessing internal memory at a desired variable access time |
09/23/1987 | EP0238039A2 Network event identifiers |
09/23/1987 | EP0237745A2 Coding of acyclic list data structures for information retrieval |
09/23/1987 | EP0237637A2 A method for the relocation of linked control blocks |
09/22/1987 | US4695951 Computer hierarchy control |
09/22/1987 | US4695950 Fast two-level dynamic address translation method and means |
09/22/1987 | US4695949 Method for efficient support for reference counting |
09/22/1987 | US4695948 Bus to bus converter using a RAM for multiple address mapping |
09/22/1987 | US4695947 Information processing system |
09/22/1987 | US4695943 Multiprocessor shared pipeline cache memory with split cycle and concurrent utilization |
09/17/1987 | DE3608659A1 Method and arrangement to protect memory areas against forbidden writing |
09/17/1987 | DE3608547A1 Computer system with external memory |
09/17/1987 | DE3602656A1 "Least recently used" network without pointer registers and comparators |
09/16/1987 | EP0237324A2 Computer-controlled document data filing system |
09/16/1987 | EP0236743A2 Method for restarting a long-running, fault-tolerant operation in a transaction-oriented data base system |
09/16/1987 | EP0236717A2 Method for choosing replacement lines in a two-dimensionally redundant array |
09/16/1987 | EP0236615A2 Functional units for computers |
09/16/1987 | EP0120914B1 Multiprocessor computing system featuring shared global control |
09/15/1987 | US4694454 Dynamic memory diagnosis and error correction apparatus |
09/15/1987 | US4694395 Data processing system |
09/15/1987 | CA1226962A1 Masked data fetch and modifying device |
09/15/1987 | CA1226959A1 Cache coherence system |
09/15/1987 | CA1226953A1 Lsi microprocessor chip with backward pin compatibility |
09/15/1987 | CA1226943A1 Method for storing digital information |
09/15/1987 | CA1226942A1 Apparatus and method for testing and verifying the refresh logic of dynamic mos memories |
09/09/1987 | EP0235525A2 Statistical information access system |
09/09/1987 | EP0235255A1 Data processing system including a prefetch circuit. |
09/08/1987 | US4692922 Method for correcting and detecting errors |
09/08/1987 | CA1226673A1 Reconfigurable memory system |
09/02/1987 | EP0234937A2 Tag buffer with testing capability |
09/02/1987 | EP0234617A1 Data processing arrangement containing a memory device equipped with a coincidence circuit which can be switched in an error recognition and a coincidence mode and method therefor |
09/02/1987 | EP0234598A2 Interface circuit for subsystem controller |
09/02/1987 | EP0234038A2 Apparatus for identifying the LRU storage unit in a memory |
09/02/1987 | CN87102176A Apparatus and method for providing distributed control in main memory unit of data processing system |
09/01/1987 | US4691350 Security device for stored sensitive data |
09/01/1987 | US4691282 16-bit microprocessor system |
09/01/1987 | US4691281 Data processing system simultaneously carrying out address translation of a plurality of logical addresses |
09/01/1987 | US4691279 Instruction buffer for a digital data processing system |
09/01/1987 | US4691277 Small instruction cache using branch target table to effect instruction prefetch |
09/01/1987 | CA1226372A1 Address translation control system |
08/26/1987 | EP0233783A1 Apparatus for recording and/or reproducing data |
08/26/1987 | EP0107715B1 Memory addressing system |
08/25/1987 | US4689824 Image rotation method |
08/25/1987 | US4689786 Local area network with self assigned address method |
08/19/1987 | EP0232960A2 Method for automatically extending the size of a segment in a page segmented virtual memory data processing system |
08/19/1987 | EP0232769A2 Maintaining availability of a restartable data base system |
08/19/1987 | EP0232526A2 Paged virtual cache system |
08/19/1987 | EP0232518A2 Address mapping method and system for controlling a working memory |
08/18/1987 | US4688219 Semiconductor memory device having redundant memory and parity capabilities |
08/18/1987 | US4688197 Control of data access to memory for improved video system |
08/18/1987 | US4688188 Data storage apparatus for storing groups of data with read and write request detection |
08/18/1987 | US4688172 Initialization apparatus for a data processing system with a plurality of input/output and storage controller connected to a common bus |
08/18/1987 | US4688034 Paging receiver and transmitting device adapted to said receiver |
08/18/1987 | CA1225749A1 Data processing system with a plurality of processors accessing a common bus to interleaved storage |
08/13/1987 | WO1987004826A1 Multi-processor apparatus |
08/13/1987 | WO1987004825A1 Apparatus and method for providing distributed control in a main memory unit of a data processing system |
08/13/1987 | WO1987004823A1 Apparatus and method for providing a cache memory unit with a write operation utilizing two system clock cycles |
08/13/1987 | WO1987004822A1 Apparatus and method for addressing semiconductor arrays in a main memory unit on consecutive system clock cycles |
08/13/1987 | WO1987003395A3 Computer stack arrangement |
08/13/1987 | DE3603723A1 Arrangement to form a supplementary address line to trigger a working memory |
08/12/1987 | EP0231686A2 Cellular array processing apparatus with variable nesting depth vector processor control structure |
08/12/1987 | EP0231574A2 Cache-based computer systems |
08/12/1987 | EP0231472A2 Editing system for virtual machines |
08/12/1987 | EP0231438A2 Information recording system |