| Patents for G06F 12 - Accessing, addressing or allocating within memory systems or architectures (152,539) |
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| 07/27/1995 | CA2181926A1 Apparatus and method for controlling access to and interconnection of computer system resources |
| 07/26/1995 | EP0664510A2 Method and system for aggregating objects |
| 07/26/1995 | EP0664045A1 Target management method for data backup to a shared transfer station, multiple media element device |
| 07/26/1995 | EP0664030A1 Double buffering operations between the memory bus and the expansion bus of a computer system |
| 07/26/1995 | EP0664029A1 Computer failure recovery and alert system |
| 07/26/1995 | EP0579633B1 Method of compiling, by computer, a programme consisting of several parts |
| 07/25/1995 | US5437049 Reduction processor employing an active associative memory |
| 07/25/1995 | US5437029 Path name resolution method providing fixed speed of file accessing in computer network |
| 07/25/1995 | US5437028 File management system with file-size flexibility |
| 07/25/1995 | US5437027 System and method for database management supporting object-oriented programming |
| 07/25/1995 | US5437026 Removing uncommitted changes made to stored data by a database management system |
| 07/25/1995 | US5437022 Storage controller having additional cache memory and a means for recovering from failure and reconfiguring a control unit thereof in response thereto |
| 07/25/1995 | US5437019 Addressing method and apparatus for a computer system |
| 07/25/1995 | US5437018 Emulation of semiconductor and magnetic auxiliary storage devices with semiconductor memory |
| 07/25/1995 | US5437017 Method and system for maintaining translation lookaside buffer coherency in a multiprocessor data processing system |
| 07/25/1995 | US5437016 Apparatus and method for translating logical addresses for virtual machines |
| 07/25/1995 | US5436972 Method for preventing inadvertent betrayal by a trustee of escrowed digital secrets |
| 07/25/1995 | US5436869 Memory controller which can carry out a high speed access when supplied with input addresses with a time interval left between the input addresses having the same row address |
| 07/25/1995 | US5436856 Self testing computer system with circuits including test registers |
| 07/20/1995 | WO1995019608A1 A secure application card for sharing application data and procedures among a plurality of microprocessors |
| 07/20/1995 | WO1995019607A1 A secure memory card with programmed controlled security access control |
| 07/20/1995 | WO1995019601A2 Optimized database management system |
| 07/20/1995 | WO1995019599A1 File backup system |
| 07/20/1995 | WO1995019593A1 A computer security system |
| 07/19/1995 | EP0663761A2 Cipher data communications apparatus |
| 07/19/1995 | EP0663641A1 Summary catalogs |
| 07/19/1995 | EP0663640A1 Replication facility |
| 07/19/1995 | EP0663636A1 Logically addressable physical memory for a virtual memory computer system that supports multiple page sizes |
| 07/19/1995 | EP0663087A1 Method and apparatus for non-snoop window reduction |
| 07/19/1995 | EP0663084A1 Fault tolerant memory system |
| 07/19/1995 | EP0663083A1 System and method for handling load and/or store operations in a superscalar microprocessor |
| 07/19/1995 | EP0366757B1 Memory selftest method and apparatus |
| 07/18/1995 | US5435001 Method of state determination in lock-stepped processors |
| 07/18/1995 | US5435000 Central processing unit using dual basic processing units and combined result bus |
| 07/18/1995 | US5434994 System and method for maintaining replicated data coherency in a data processing system |
| 07/18/1995 | US5434993 Methods and apparatus for creating a pending write-back controller for a cache controller on a packet switched memory bus employing dual directories |
| 07/18/1995 | US5434992 Method and means for dynamically partitioning cache into a global and data type subcache hierarchy from a real time reference trace |
| 07/18/1995 | US5434990 Method for serially or concurrently addressing n individually addressable memories each having an address latch and data latch |
| 07/18/1995 | US5434989 Cache memory for efficient access with address selectors |
| 07/18/1995 | US5434988 Data processor implementing a two's complement addressing technique |
| 07/18/1995 | US5434982 Electronically configurable connection device |
| 07/18/1995 | US5434868 Fault tolerant memory |
| 07/18/1995 | US5434819 Semiconductor memory device having an automatically activated verify function capability |
| 07/13/1995 | WO1995019004A1 Data memory and processor bus |
| 07/13/1995 | WO1995019003A1 File transfer method and apparatus using hash numbers |
| 07/13/1995 | WO1995019002A1 Method and device for backing up and/or archiving data and/or computer files |
| 07/13/1995 | WO1995018998A1 Safe-stop mode for a microprocessor operating in a pseudo-static random access memory environment |
| 07/13/1995 | WO1995018997A2 Virtual memory management system and method using data compression |
| 07/13/1995 | WO1995018996A2 Lossless data compression system and method |
| 07/13/1995 | CA2180459A1 File transfer method and apparatus using hash numbers |
| 07/13/1995 | CA2179736A1 Method and device for backing up and/or archiving data and/or computer files |
| 07/13/1995 | CA2157595A1 Safe-stop mode for a microprocessor operating in a pseudo-static random access memory environment |
| 07/12/1995 | EP0662663A2 Semiconductor memory with built-in cache |
| 07/12/1995 | EP0662227A1 Computer system memory management method, and computer system and memory using said method |
| 07/12/1995 | CN1105136A 信息处理系统 The information processing system |
| 07/11/1995 | US5432950 System for securing a data processing system and method of operation |
| 07/11/1995 | US5432947 Power control technique for a computer system to provide adjustable storage and non-storage access times and an adjustable processor idle time |
| 07/11/1995 | US5432939 Trusted personal computer system with management control over initial program loading |
| 07/11/1995 | US5432929 Storage subsystem having a modifiable key-lock |
| 07/11/1995 | US5432926 Method and apparatus for improving database reliability and response time in a distributed transaction processing system |
| 07/11/1995 | US5432922 Digital storage system and method having alternating deferred updating of mirrored storage disks |
| 07/11/1995 | US5432919 Sequential reference management for cache memories |
| 07/11/1995 | US5432918 Method and apparatus for ordering read and write operations using conflict bits in a write queue |
| 07/11/1995 | US5432917 Tabulation of multi-bit vector history |
| 07/11/1995 | US5432908 High speed buffer management of share memory using linked lists and plural buffer managers for processing multiple requests concurrently |
| 07/11/1995 | US5432849 In a data storage system |
| 07/11/1995 | US5432823 Method and circuitry for minimizing clock-data skew in a bus system |
| 07/11/1995 | US5432804 Digital processor and viterbi decoder having shared memory |
| 07/11/1995 | US5432802 Information processing device having electrically erasable programmable read only memory with error check and correction circuit |
| 07/11/1995 | US5432748 Solid state peripheral storage device |
| 07/11/1995 | US5432742 System memory and a microcomputer comprising the same |
| 07/11/1995 | US5432733 Semiconductor memory device |
| 07/11/1995 | CA2072590C Security device having a memory and/or a microcomputer for data processing hardware |
| 07/11/1995 | CA2050405C Temporary information storage system incorporating a buffer memory for fixed or variable length data blocks |
| 07/06/1995 | WO1995018407A1 Solid state memory system |
| 07/06/1995 | WO1995018406A1 Frame structure which provides an interface between parts of a compound document |
| 07/05/1995 | EP0661653A1 Method and system for tracking attributes of files |
| 07/05/1995 | EP0661652A1 Distributed file system |
| 07/05/1995 | EP0661651A1 Unification of directory service with file system services |
| 07/05/1995 | EP0661642A2 Microcomputer with memory read protection |
| 07/05/1995 | EP0661641A2 A computer system |
| 07/05/1995 | EP0661640A1 System and method for accessing data in a computer system including a cache controller and a memory controller connected in parallel |
| 07/05/1995 | EP0661639A1 Data prefetch in mass data storage systems |
| 07/05/1995 | EP0661638A1 Method and apparatus for transferring data in a computer |
| 07/05/1995 | EP0661637A1 Configuration and RAM/ROM control of daughter card residing on adapter card |
| 07/05/1995 | EP0661635A1 A system and method for controlling command queuing on parity drives in an array of disk drives |
| 07/05/1995 | EP0660954A1 Multiported buffer memory system for disk drive complex |
| 07/05/1995 | EP0660953A1 Data processing system with reduced look-up table for a function with non-uniform resolution |
| 07/05/1995 | CN1104786A 信息处理系统 The information processing system |
| 07/04/1995 | US5430888 Pipeline utilizing an integral cache for transferring data to and from a register |
| 07/04/1995 | US5430884 Scalar/vector processor |
| 07/04/1995 | US5430870 In a computer system |
| 07/04/1995 | US5430869 System and method for restructuring a B-Tree |
| 07/04/1995 | US5430868 Shared memory with benign failure modes |
| 07/04/1995 | US5430867 Data processing system having a resume function and an operating method thereof |
| 07/04/1995 | US5430866 Method and apparatus for deriving mirrored unit state when re-initializing a system |
| 07/04/1995 | US5430864 Extending computer architecture from 32-bits to 64-bits by using the most significant bit of the stack pointer register to indicate word size |
| 07/04/1995 | US5430861 Computer using optically encoded virtual memory |
| 07/04/1995 | US5430859 For use with a computer system |
| 07/04/1995 | US5430857 Method and apparatus for translating logical addresses into physical addresses using odd/even translation tables |