Patents
Patents for G06F 12 - Accessing, addressing or allocating within memory systems or architectures (152,539)
08/1995
08/29/1995CA2003571C Communication command control system between cpus
08/24/1995WO1995022803A2 Circuit and method for detecting segment limit errors for code fetches
08/24/1995WO1995022796A1 Method and apparatus for retrieving secure information from a cd-rom database
08/24/1995WO1995022795A2 Method and apparatus for detecting memory segment violations in a computer system
08/24/1995WO1995022792A1 A method and apparatus for controlling access to a database
08/24/1995WO1995022791A2 Method and apparatus for single cycle cache access on double word boundary cross
08/23/1995EP0668578A2 System for storing and selectively transferring of personal data
08/23/1995EP0668565A1 Virtual memory system
08/23/1995EP0668560A2 Coexecuting method and means for performing parallel processing in conventional types of data processing systems
08/23/1995EP0668556A2 A queue memory system and method therefor
08/23/1995EP0668555A2 Method and apparatus for reclaiming data storage volumes in a data storage library
08/23/1995CN1107246A Structure and enclosure assembly for a disk drive
08/22/1995US5444852 I/O device interface having buffer mapped in processor memory addressing space and control registers mapped in processor I/O addressing space
08/22/1995US5444851 Method of accessing configured nodes in a facilities management system with a non-configured device
08/22/1995US5444780 Client/server based secure timekeeping system
08/22/1995US5444652 Semiconductor memory device having a memory cell unit including a plurality of transistors connected in series
08/22/1995US5444646 Fully static 32 bit alu with two stage carry bypass
08/22/1995US5444489 Vector quantization video encoder using hierarchical cache memory scheme
08/17/1995WO1995022126A1 Data exchange system comprising portable data processing units
08/17/1995WO1995022111A1 Distributed data base system
08/17/1995WO1995022109A1 Method and device to control a memory
08/17/1995WO1995022105A1 Back-up method for equipment settings
08/17/1995WO1995022104A1 Use of multiple applications and allocation of memory or other resources in a gui environment
08/17/1995CA2466650A1 Data exchange system comprising portable data processing units
08/17/1995CA2142434A1 Storage and selective information transmission system for personal data
08/16/1995EP0667585A1 Graphical user interface
08/16/1995EP0667580A2 Cache System for a memory
08/16/1995EP0667579A1 Cache for optical storage device
08/16/1995EP0667578A2 Double cache snoop mechanism
08/16/1995EP0667576A1 A data processor and a trace circuit using the data processor
08/16/1995EP0667569A1 Improvements in or relating to mask generation
08/16/1995CN1106959A Power regulation for redundant battery supplies
08/16/1995CN1106951A Fully integrated cache architecture
08/15/1995US5442802 Asynchronous co-processor data mover method and means
08/15/1995US5442770 Triple port cache memory
08/15/1995US5442768 Recording and reproducing data using batch erasable nonvolatile semiconductor memories capable of selectively erasing one of a plurality of data groups stored in one of the memories
08/15/1995US5442766 Method and system for distributed instruction address translation in a multiscalar data processing system
08/15/1995US5442765 Database system which adjusts the data storage order based on the processing speed of the storage media
08/15/1995US5442760 Decoded instruction cache architecture with each instruction field in multiple-instruction cache line directly connected to specific functional unit
08/15/1995US5442748 Architecture of output switching circuitry for frame buffer
08/15/1995US5442747 Flexible multiport multiformat burst buffer
08/15/1995US5442704 Secure memory card with programmed controlled security access control
08/15/1995US5442645 Method for checking the integrity of a program or data, and apparatus for implementing this method
08/15/1995US5442611 Method of recording information on record medium having data record region and file management information record region
08/15/1995US5442579 Combined multiplier and accumulator
08/15/1995US5442571 Method and apparatus for cache miss reduction by simulating cache associativity
08/15/1995US5442350 Method and means providing static dictionary structures for compressing character data and expanding compressed data
08/15/1995US5442342 Distributed user authentication protocol
08/15/1995CA2024444C Process using virtual addressing in a non-privileged instruction to control the copying of a page of data in or between multiple media
08/15/1995CA2020520C Apparatus and method for preventing unauthorized modification to bios in a personal computer system
08/10/1995WO1995021413A1 Data processing installation with a controller-addressable working memory
08/10/1995WO1995021407A2 Improved method and apparatus for data access in multiprocessor digital data processing systems
08/10/1995WO1995018996A3 Lossless data compression system and method
08/10/1995DE4403791A1 Datenverarbeitungsanlage Data processing system
08/10/1995CA2180252A1 Improved method and apparatus for data access in multiprocessor digital data processing systems
08/09/1995EP0666684A2 Data converting device
08/09/1995EP0666550A1 Data exchange system comprising portable data processing units
08/09/1995EP0666539A2 Cache control system
08/09/1995EP0666536A1 Dump method, controller, and information processing system
08/09/1995EP0666535A2 A method and apparatus for detecting memory access errors
08/09/1995EP0666199A1 Interface circuit between two different busses in a vehicle
08/09/1995EP0665979A1 Verifiable security circuitry for preventing unauthorized access to programmed read only memory.
08/09/1995EP0665968A1 A system for operating application software in a safety critical environment
08/09/1995EP0635149A4 Method and apparatus for storing and retrieving multi-dimensional data in computer memory.
08/09/1995EP0386461B1 Fault tolerant computer memory system with disablement feature
08/09/1995CN1106560A Fault tolerant memory system
08/08/1995US5440757 Data processor having multistage store buffer for processing exceptions
08/08/1995US5440752 Microprocessor architecture with a switch network for data transfer between cache, memory port, and IOU
08/08/1995US5440751 Burst data transfer to single cycle data transfer conversion and strobe signal conversion
08/08/1995US5440749 High performance, low cost microprocessor architecture
08/08/1995US5440731 Method of detecting unjustifiable reloading of stored data
08/08/1995US5440728 Information processing apparatus
08/08/1995US5440717 Computer pipeline including dual-ported, content-addressable writebuffer
08/08/1995US5440712 Database input/output control system having nonvolatile storing unit for maintaining the database
08/08/1995US5440710 Emulation of segment bounds checking using paging with sub-page validity
08/08/1995US5440708 Microprocessor and storage management system having said microprocessor
08/08/1995US5440707 Instruction and data cache with a shared TLB for split accesses and snooping in the same clock cycle
08/08/1995US5440705 Address modulo adjust unit for a memory management unit for monolithic digital signal processor
08/08/1995US5440698 Arbitration of packet switched busses, including busses for shared memory multiprocessors
08/08/1995US5440696 Data processing device for reducing the number of internal bus lines
08/08/1995US5440693 Personal computer with drive identification
08/08/1995US5440686 Selecting a data unit candidate to be demoted to a backing store from a front store based upon thresholds individual to each of the data candidates
08/08/1995US5440523 Multiple-port shared memory interface and associated method
08/05/1995CA2140084A1 Method and apparatus for detecting memory access errors
08/03/1995WO1995020792A1 Improved method and apparatus for accessing a database
08/03/1995CA2180449A1 Improved method and apparatus for accessing a database
08/02/1995EP0665670A2 Remote file transfer method and apparatus
08/02/1995EP0665499A2 Hierarchic data storage system
08/02/1995EP0665497A1 Method and apparatus for a multilayer system quiescent suspend and resume operation
08/02/1995EP0665495A2 A distributed lock manager using a passive, state-full control-server
08/02/1995EP0442651B1 Apparatus and method for background memory test during system start up
08/02/1995EP0377164B1 LRU error detection using the collection of read and written LRU bits
08/01/1995US5438670 Method of prechecking the validity of a write access request
08/01/1995US5438663 External interface for a high performance graphics adapter allowing for graphics compatibility
08/01/1995US5438535 Content addressable memory system
08/01/1995US5438281 Semiconductor integrated circuit device and data processing system having an interface with reduced parasitic capacitance
08/01/1995CA2037021C Physical database design system
07/1995
07/27/1995WO1995020279A1 Apparatus and method for controlling access to and interconnection of computer system resources
07/27/1995WO1995014970A3 A fault tolerant queue system
07/27/1995DE19501560A1 Image processing circuit for graphics data