| Patents for G06F 12 - Accessing, addressing or allocating within memory systems or architectures (152,539) |
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| 07/10/1998 | CA2194304A1 Caveat |
| 07/09/1998 | WO1998029986A1 Hash-based translation method and apparatus with multiple level collision resolution |
| 07/09/1998 | WO1998029981A1 Method and apparatus for secure storage of data |
| 07/09/1998 | WO1998029843A1 Dynamic data interpretation method for a chip card |
| 07/09/1998 | WO1998029838A1 Tiled linear host texture storage |
| 07/09/1998 | WO1998029816A1 Method and apparatus for combining a volatile and a nonvolatile memory array |
| 07/09/1998 | WO1998029815A1 Ic card |
| 07/09/1998 | WO1998029813A1 Method for ensuring the safety of a security module, and related security module |
| 07/09/1998 | WO1998029812A1 Selectable bit width cache memory system and method |
| 07/09/1998 | WO1998029806A1 A system and method for execution management of computer programs |
| 07/09/1998 | WO1998029803A1 Method for loading an application programme in a chip card |
| 07/09/1998 | WO1998029799A1 System and method for reordering lookup table entries when table address bits are reordered |
| 07/09/1998 | WO1998029798A1 System and method for reordering lookup table entries when table address bits are inverted |
| 07/09/1998 | WO1998021712A3 Method and apparatus utilizing a region based page table walk bit |
| 07/09/1998 | WO1998010611A3 System for preventing electronic memory tampering |
| 07/09/1998 | CA2276716A1 Method for loading an application programme in a chip card |
| 07/09/1998 | CA2275968A1 Ic card |
| 07/09/1998 | CA2275940A1 Dynamic data interpretation method for a chip card |
| 07/09/1998 | CA2247475A1 Method for ensuring the safety of a security module, and related security module |
| 07/08/1998 | EP0852380A2 Variable latency memory circuit |
| 07/08/1998 | EP0852355A2 Programmable controller |
| 07/08/1998 | EP0852035A1 A high availability computer system and methods related thereto |
| 07/08/1998 | EP0642690B1 Multi-source video synchronization |
| 07/08/1998 | EP0541288B1 Circuit module redundacy architecture |
| 07/08/1998 | CN1187279A Intelligent memory management system and method |
| 07/07/1998 | USRE35839 CD-ROM disk and security check method for the same |
| 07/07/1998 | US5778447 System and method for fast memory access using speculative access in a bus architecture system |
| 07/07/1998 | US5778444 Method and apparatus for reset-sensitive and controlled register write accesses in a data processing system with user and test modes |
| 07/07/1998 | US5778443 Method and apparatus for conserving power and system resources in a computer system employing a virtual memory |
| 07/07/1998 | US5778438 Method and apparatus for maintaining cache coherency in a computer system with a highly pipelined bus and multiple conflicting snoop requests |
| 07/07/1998 | US5778437 Invalidation bus optimization for multiprocessors using directory-based cache coherence protocols in which an address of a line to be modified is placed on the invalidation bus simultaneously with sending a modify request to the directory |
| 07/07/1998 | US5778436 Predictive caching system and method based on memory access which previously followed a cache miss |
| 07/07/1998 | US5778435 History-based prefetch cache including a time queue |
| 07/07/1998 | US5778434 System and method for processing multiple requests and out of order returns |
| 07/07/1998 | US5778433 Computer system including a first level write-back cache and a second level cache |
| 07/07/1998 | US5778432 In a data processing system |
| 07/07/1998 | US5778431 Computer system |
| 07/07/1998 | US5778430 Method and apparatus for computer disk cache management |
| 07/07/1998 | US5778429 Parallel processor system including a cache memory subsystem that has independently addressable local and remote data areas |
| 07/07/1998 | US5778428 Programmable high performance mode for multi-way associative cache/memory designs |
| 07/07/1998 | US5778427 Method and apparatus for selecting a way of a multi-way associative cache by storing waylets in a translation structure |
| 07/07/1998 | US5778426 Methods and structure to maintain a two level cache in a RAID controller and thereby selecting a preferred posting method |
| 07/07/1998 | US5778425 Electronic system having a first level write through cache memory and smaller second-level write-back cache memory and method of operating the same |
| 07/07/1998 | US5778424 Distributed placement, variable-size cache architecture |
| 07/07/1998 | US5778423 Prefetch instruction for improving performance in reduced instruction set processor |
| 07/07/1998 | US5778422 Data processing system memory controller that selectively caches data associated with write requests |
| 07/07/1998 | US5778419 DRAM with high bandwidth interface that uses packets and arbitration |
| 07/07/1998 | US5778413 Programmable memory controller having two level look-up for memory timing parameter |
| 07/07/1998 | US5778408 For improving operations of a spreadsheet computer program |
| 07/07/1998 | US5778407 Methods and apparatus for determining operating characteristics of a memory element based on its physical location |
| 07/07/1998 | US5778395 System for backing up files from disk volumes on multiple nodes of a computer network |
| 07/07/1998 | US5778392 Opportunistic tile-pulling, vacancy-filling method and apparatus for file-structure reorganization |
| 07/07/1998 | US5778388 Method of processing a synchronization point in a database management system to assure a database version using update logs from accumulated transactions |
| 07/07/1998 | US5778384 Virtual file system accessing subsystem used with a computer system |
| 07/07/1998 | US5778365 File management device |
| 07/07/1998 | US5778354 Database management system with improved indexed accessing |
| 07/07/1998 | US5778349 Method of processing input/output request in computer system including a plurality of subsystems |
| 07/07/1998 | US5778243 In a multi-threaded computer system |
| 07/07/1998 | US5778199 Blocking address enable signal from a device on a bus |
| 07/07/1998 | US5778197 Method for allocating system resources in a hierarchical bus structure |
| 07/07/1998 | US5778186 Data serving apparatus with access requests quantized into variable size data and time quantization units |
| 07/07/1998 | US5778179 System for flexible distributed processing and transaction processing suitable for nested transaction |
| 07/07/1998 | US5778171 Processor interface chip for dual-microprocessor processor system |
| 07/07/1998 | US5778168 Transaction device driver technique for a journaling file system to ensure atomicity of write operations to a computer mass storage device |
| 07/07/1998 | US5778140 Video signal processing apparatus |
| 07/07/1998 | US5778070 Method and apparatus for protecting flash memory |
| 07/07/1998 | US5777942 Semiconductor memory device including dynamic type memory and static type memory formed on the common chip and an operating method thereof |
| 07/07/1998 | US5777632 For a memory |
| 07/07/1998 | US5777628 Method and apparatus for detecting cache collisions in a two dimensional memory |
| 07/07/1998 | US5777608 Apparatus and method for in-parallel scan-line graphics rendering using content-searchable memories |
| 07/06/1998 | WO1998030947A2 An apparatus and method for retrieving information using standard objects |
| 07/02/1998 | WO1998028940A1 Management of data structures |
| 07/02/1998 | WO1998028714A1 Enhanced texture map data fetching circuit and method |
| 07/02/1998 | WO1998028685A1 Coordinating shared access to common storage |
| 07/02/1998 | WO1998013740A3 Method and apparatus for aliasing memory data in an advanced microprocessor |
| 07/02/1998 | CA2275727A1 Enhanced texture map data fetching circuit and method |
| 07/02/1998 | CA2241883A1 Management of data structures |
| 07/01/1998 | EP0851425A2 Method and apparatus for using EDO memory devices in a memory system designed for FPM memory devices |
| 07/01/1998 | EP0851391A2 Data hiding and extracting method and system |
| 07/01/1998 | EP0851366A1 Modified indirect addressing for file system |
| 07/01/1998 | EP0851359A1 Memory with read-protected zones |
| 07/01/1998 | EP0851358A2 Processing system security |
| 07/01/1998 | EP0851357A1 Method and apparatus for preloading different default address translation attributes |
| 07/01/1998 | EP0851356A2 Multiprocessor computer system |
| 07/01/1998 | EP0851355A2 Cache-efficient object loader |
| 07/01/1998 | EP0851354A2 Reorganization of collisions in a hash bucket of a hash table to improve system performance |
| 07/01/1998 | EP0851353A1 Memory management in a computer system |
| 07/01/1998 | EP0851344A2 Combined branch prediction and cache prefetch in a microprocessor |
| 07/01/1998 | EP0851339A2 A storage system capable of relocating data |
| 07/01/1998 | EP0850454A1 Identifying changes in on-line data repositories |
| 07/01/1998 | EP0850452A1 Controlling shared disk data in a duplexed computer unit |
| 07/01/1998 | EP0764303B1 Method of ensuring the security of microcontrollers |
| 07/01/1998 | CN1186275A IC circuit device |
| 06/30/1998 | US5774735 System resource enable method with wake-up feature |
| 06/30/1998 | US5774715 File system level compression using holes |
| 06/30/1998 | US5774700 Method and apparatus for determining the timing of snoop windows in a pipelined bus |
| 06/30/1998 | US5774699 System controller for controlling switching operations of various operation clocks for CPU, DRAM, and the like |
| 06/30/1998 | US5774685 Method and apparatus for biasing cache LRU for prefetched instructions/data based upon evaluation of speculative conditions |
| 06/30/1998 | US5774682 System for concurrent cache data access by maintaining and selectively merging multiple ranked part copies |
| 06/30/1998 | US5774656 Information processing system and method and service supplying method for use within a network |