Patents
Sitemap › G06 - Computing; Calculating; Counting › G06F - Electric digital data processing › G06F 12 - Accessing, addressing or allocating within memory systems or architectures
Patents for G06F 12 - Accessing, addressing or allocating within memory systems or architectures (152,539)
06/1998
06/09/1998US5765212 Memory control circuit that selectively performs address translation based on the value of a road start address
06/09/1998US5765211 Segmenting non-volatile memory into logical pages sized to fit groups of commonly erasable data
06/09/1998US5765210 Allocation of real storage for hardware descriptors within virtual memory that are associated with on-line storage increments
06/09/1998US5765209 Method and apparatus to eliminate redundant mapping in a TLB utilizing variable sized pages
06/09/1998US5765208 Method of speculatively executing store instructions prior to performing snoop operations
06/09/1998US5765207 Recursive hardware state machine
06/09/1998US5765206 System and method for emulating a segmented virtual address space by a microprocessor that provides a non-segmented virtual address space
06/09/1998US5765205 Method and system for on-demand software distribution
06/09/1998US5765204 Computer program product
06/09/1998US5765201 Changing page size in storage media of computer system
06/09/1998US5765199 Data processor with alocate bit and method of operation
06/09/1998US5765198 Transparent relocation of real memory addresses in the main memory of a data processor
06/09/1998US5765197 Method and system for authentication of a memory unit for a computer system
06/09/1998US5765196 System and method for servicing copyback requests in a multiprocessor system with a shared memory
06/09/1998US5765195 Method for distributing interprocessor interrupt requests via cache memory coherency mechanisms
06/09/1998US5765194 Timing consistent dynamic compare with force miss circuit
06/09/1998US5765193 System for controlling a write operation involving data held in a write cache
06/09/1998US5765192 Method and computer program product to reuse directory search handles
06/09/1998US5765191 Method for implementing a four-way least recently used (LRU) mechanism in high-performance
06/09/1998US5765190 Cache memory in a data processing system
06/09/1998US5765189 Method and apparatus for computer disk drive buffer management
06/09/1998US5765188 Memory presence and type detection using multiplexed memory select line
06/09/1998US5765185 EEPROM array with flash-like core having ECC or a write cache or interruptible load cycles
06/09/1998US5765183 Disk array subsystem and data generation method therefor
06/09/1998US5765181 System and method of addressing distributed memory within a massively parallel processing system
06/09/1998US5765174 In a computer system
06/09/1998US5765170 Computer program
06/09/1998US5765167 Data file update processing apparatus
06/09/1998US5765157 Computer system and method for executing threads of execution with reduced run-time memory space requirements
06/09/1998US5765156 Data transfer with expanded clipboard formats
06/09/1998US5765153 Information handling system, method, and article of manufacture including object system authorization and registration
06/09/1998US5765151 System and method for file system fix-on-panic for a computer operating system
06/09/1998US5765148 Database processing apparatus and database processing method for variable length objects, and computer-readable memory medium for storing database processing program
06/09/1998US5765036 Virtual media system
06/09/1998US5765035 Recorder buffer capable of detecting dependencies between accesses to a pair of caches
06/09/1998US5765022 System for transferring data from a source device to a target device in which the address of data movement engine is determined
06/09/1998US5765020 Method of transferring data by transmitting lower order and upper odermemory address bits in separate words with respective op codes and start information
06/09/1998US5764999 Enhanced system management mode with nesting
06/09/1998US5764978 Database system having a hierarchical network database and a corresponding relational database
06/09/1998US5764969 Method and system for enhanced management operation utilizing intermixed user level and supervisory level instructions with partial concept synchronization
06/09/1998US5764968 Computer system
06/09/1998US5764964 Device for protecting selected information in multi-media workstations
06/09/1998US5764950 Microcomputer
06/09/1998US5764946 Superscalar microprocessor employing a way prediction unit to predict the way of an instruction fetch address and to concurrently provide a branch prediction address corresponding to the fetch address
06/09/1998US5764945 CD-ROM average access time improvement
06/09/1998US5764944 Method and apparatus for TLB invalidation mechanism for protective page fault
06/09/1998US5764935 High speed active bus
06/09/1998US5764930 Method and apparatus for providing reset transparency on a reconfigurable bus
06/09/1998US5764922 I/O system for off-loading operating system functions
06/09/1998US5764889 Method and apparatus for creating a security environment for a user task in a client/server system
06/09/1998US5764878 Built-in self repair system for embedded memories
06/09/1998US5764761 Eletronic assembly with integrated circuit devices including lock circuitry
06/09/1998US5764591 Memory device and memory control circuit
06/09/1998US5764587 Static wordline redundancy memory device
06/09/1998US5764577 Fusleless memory repair system and method of operation
06/04/1998WO1998024029A1 Flash memory mass storage system
06/04/1998WO1998024028A1 Method and system for managing a flash memory mass storage system
06/04/1998WO1998013763A3 Multiport cache memory with address conflict detection
06/04/1998WO1998012704A3 Nonvolatile writeable memory with program suspend command
06/04/1998WO1997042558A3 A device driver for accessing computer files
06/04/1998DE19752443A1 Sequence control circuit for test pattern generator of semiconductor memory test device
06/04/1998DE19718103A1 Data transmission system authorise method e.g. for telebanking
06/04/1998CA2213591A1 System and method for voiced interface with hyperlinked information
06/03/1998EP0845757A2 Data hiding method and data extracting method
06/03/1998EP0845181A1 Link scheduling
06/03/1998EP0845120A1 General purpose, programmable media processor
06/03/1998EP0799548B1 Television set with a plurality of signal processing devices
06/03/1998EP0700540A4 Pipelined data ordering system
06/03/1998EP0654168A4 Fault-tolerant, high-speed bus system and bus interface for wafer-scale integration.
06/03/1998EP0617362B1 Data back-up in data processing system
06/03/1998EP0528585B1 Data processing system with internal instruction cache
06/03/1998CN1183841A System and method for secure transaction management and electronic rights protection
06/03/1998CN1183685A Encryption decoding method. record reproduction device and record medium
06/02/1998US5761741 Technique for addressing a partial word and concurrently providing a substitution field
06/02/1998US5761740 Method of and apparatus for rapidly loading addressing registers
06/02/1998US5761738 Computer system which stores management or control information in different address space but same offset as corresponding data
06/02/1998US5761735 Circuit for synchronizing data transfers between two devices operating at different speeds
06/02/1998US5761734 Token-based serialisation of instructions in a multiprocessor system
06/02/1998US5761733 Data storage device with security system and ferroelectric data input section
06/02/1998US5761732 Interleaving for memory cards
06/02/1998US5761729 Validation checking of shared memory accesses
06/02/1998US5761728 Asynchronous access system controlling processing modules making requests to a shared system memory
06/02/1998US5761726 Base address generation in a multi-processing system having plural memories with a unified address space corresponding to each processor
06/02/1998US5761725 Cache-based computer system employing a peripheral bus interface unit with cache write-back suppression and processor-peripheral communication suppression for data coherency
06/02/1998US5761724 Write-invalidate cache system for a split transaction bus based shared memory multiprocessor
06/02/1998US5761722 Method and apparatus for solving the stale data problem occurring in data access performed with data caches
06/02/1998US5761721 Method and system for cache coherence despite unordered interconnect transport
06/02/1998US5761720 Pixel engine pipeline processor data caching mechanism
06/02/1998US5761719 On-chip memory map for processor cache macro
06/02/1998US5761718 Conditional data pre-fetching in a device controller
06/02/1998US5761717 For a computer system
06/02/1998US5761716 Rate based memory replacement mechanism for replacing cache entries when the cache is full
06/02/1998US5761715 Information processing device and cache memory with adjustable number of ways to reduce power consumption based on cache miss ratio
06/02/1998US5761714 Single-cycle multi-accessible interleaved cache
06/02/1998US5761713 System for a computer
06/02/1998US5761712 Data memory unit and method for storing data into a lockable cache in one clock cycle by previewing the tag array
06/02/1998US5761710 Information apparatus with cache memory for data and data management information
06/02/1998US5761709 Write cache for servicing write requests within a predetermined address range
06/02/1998US5761708 Central processing unit of a computer
06/02/1998US5761707 High speed flexible slave interface for parallel common bus to local cache buffer
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