| Patents for G06F 12 - Accessing, addressing or allocating within memory systems or architectures (152,539) |
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| 04/14/1998 | US5740398 Program order sequencing of data in a microprocessor with write buffer |
| 04/14/1998 | US5740396 Semiconductor disk device |
| 04/14/1998 | US5740395 Method and apparatus for cleaning up a solid state memory disk storing floating sector data |
| 04/14/1998 | US5740379 Method for generating unique addresses for electrical devices from input bit patterns being verifiable for admissibility |
| 04/14/1998 | US5740367 Method and apparatus for improving the throughput of a local area network |
| 04/14/1998 | US5740355 For a computer network |
| 04/14/1998 | US5740098 Using one memory to supply addresses to an associated memory during testing |
| 04/14/1998 | US5740063 Measuring instrument |
| 04/14/1998 | CA2120055C Desktop computer system having multilevel power management |
| 04/14/1998 | CA2066295C Program processing system and method |
| 04/09/1998 | WO1998015086A1 Secure boot |
| 04/09/1998 | WO1998015058A1 Self-timed pulse control circuit |
| 04/09/1998 | WO1998014956A1 Memory array, memory cell, and sense amplifier test and characterization |
| 04/09/1998 | WO1998014955A1 Data retention test for static memory cell |
| 04/09/1998 | WO1998014951A1 Computer caching methods and apparatus |
| 04/09/1998 | WO1998014950A1 Memory block select using multiple word lines to address a single memory cell row |
| 04/09/1998 | WO1998014947A1 Memory including resistor bit-line loads |
| 04/09/1998 | WO1998014944A1 Active power supply filter |
| 04/09/1998 | WO1998014938A1 Recording/reproducing method suitable for recording/reproducing av data on/from disc, recorder and reproducer for the method, information recording disc and information processing system |
| 04/09/1998 | WO1998014895A2 A method for organizing and presenting the structure of a multimedia system and for presenting this structure to a person involved, in particular a user person or an author person, and a software package having such organization and presentation facility |
| 04/09/1998 | WO1998014879A1 Method for performing a continuous over-write of a file in a nonvolatile memory |
| 04/09/1998 | WO1998014878A1 A method of obtaining a buffer of contiguous memory and building a page table |
| 04/09/1998 | WO1998014877A1 Virtual addressing for subsystem dma |
| 04/09/1998 | WO1998014876A1 Circuit with a microprocessor and a pushdown storage |
| 04/09/1998 | WO1998014858A1 Marking of electronic documents in order to expose unauthorized publication |
| 04/09/1998 | WO1997015001A3 Risc microprocessor architecture |
| 04/09/1998 | CA2267164A1 Marking of electronic documents in order to expose unauthorized publication |
| 04/08/1998 | EP0834882A2 Memory device |
| 04/08/1998 | EP0834822A2 World wide web news retrieval system |
| 04/08/1998 | EP0834820A2 Hyper-text document preparing apparatus |
| 04/08/1998 | EP0834819A2 System, method, apparatus, and article of manufacture for providing identity-based caching services to a plurality of computer systems |
| 04/08/1998 | EP0834818A2 System, method, apparatus and article of manufacture for identity based caching |
| 04/08/1998 | EP0834816A2 Microprocessor architecture capable of supporting multiple heterogenous processors |
| 04/08/1998 | EP0834814A2 Signal-transfer system and semiconductor device for high speed data transfer |
| 04/08/1998 | EP0834812A1 A method for accessing flash memory and an automotive electronic control system |
| 04/08/1998 | EP0834811A1 Checkpoint acquistition accelerating apparatus |
| 04/08/1998 | EP0834807A1 Method and apparatus for performing efficient corba transactions |
| 04/08/1998 | EP0834141A1 Computer system for creating semantic object models from existing relational database schemas |
| 04/08/1998 | EP0834133A1 Data file authentication device |
| 04/08/1998 | EP0834132A1 Security for computer system resources |
| 04/08/1998 | EP0834131A1 Linked caches for context data search |
| 04/08/1998 | EP0834130A1 Reducing cache snooping overhead in a multilevel cache system with multiple bus masters and a shared level two cache |
| 04/08/1998 | EP0834129A1 Method and apparatus for reducing cache snooping overhead in a multilevel cache system |
| 04/08/1998 | EP0834127A1 Reduction of logging in distributed systems |
| 04/08/1998 | EP0834125A1 Error detection and correction method and apparatus |
| 04/08/1998 | EP0834122A1 Synchronisation procedure in a routing node |
| 04/08/1998 | EP0834119A1 Apparatus and method for reducing read miss latency |
| 04/08/1998 | EP0834118A1 Microprocessor using instruction field to specify expanded functionality |
| 04/08/1998 | EP0834080A1 Real-time data protection system and method |
| 04/08/1998 | CN1178377A Memory, semiconductor, data processor and computer system |
| 04/08/1998 | CN1178345A Memory management method for portable terminal |
| 04/07/1998 | US5737769 Physical memory optimization using programmable virtual address buffer circuits to redirect address requests |
| 04/07/1998 | US5737768 In a computer |
| 04/07/1998 | US5737765 Electronic system with circuitry for selectively enabling access to configuration registers used by a memory controller |
| 04/07/1998 | US5737764 Generation of memory column addresses using memory array type bits in a control register of a computer system |
| 04/07/1998 | US5737760 Microcontroller with security logic circuit which prevents reading of internal memory by external program |
| 04/07/1998 | US5737759 Method and apparatus for maintaining cache coherency in a computer system with a highly pipelined bus and multiple conflicting snoop requests |
| 04/07/1998 | US5737758 In a computer system |
| 04/07/1998 | US5737757 Cache tag system for use with multiple processors including the most recently requested processor identification |
| 04/07/1998 | US5737756 Dual bus computer network using dual busses with dual spy modules enabling clearing of invalidation queue for processor with store through cache while providing retry cycles for incomplete accesses to invalidation queue |
| 04/07/1998 | US5737755 System level mechanism for invalidating data stored in the external cache of a processor in a computer system |
| 04/07/1998 | US5737754 Cache memory which selects one of several blocks to update by digitally combining control bits in all the blocks |
| 04/07/1998 | US5737753 Least recently used block replacement for four block cache logic system |
| 04/07/1998 | US5737752 Cache replacement mechanism |
| 04/07/1998 | US5737751 Cache memory management system having reduced reloads to a second level cache for enhanced memory performance in a data processing system |
| 04/07/1998 | US5737750 Partitioned single array cache memory having first and second storage regions for storing non-branch and branch instructions |
| 04/07/1998 | US5737749 Method and system for dynamically sharing cache capacity in a microprocessor |
| 04/07/1998 | US5737748 Microprocessor unit having a first level write-through cache memory and a smaller second-level write-back cache memory |
| 04/07/1998 | US5737747 Prefetching to service multiple video streams from an integrated cached disk array |
| 04/07/1998 | US5737746 Computer system including an apparatus for reducing power consumption in an on-chip tag static RAM |
| 04/07/1998 | US5737743 Disk block controller and file system which supports large files by allocating multiple sequential physical blocks to logical blocks |
| 04/07/1998 | US5737742 Memory system using flash memory and method of controlling the memory system |
| 04/07/1998 | US5737738 Distributed read/write replication with primary copy first write and primary copy transfer features |
| 04/07/1998 | US5737737 Data management method and apparatus |
| 04/07/1998 | US5737636 Method and system for detecting bypass errors in a load/store unit of a superscalar processor |
| 04/07/1998 | US5737632 Magnetic disc control apparatus with parallel data transfer between disc control unit and encoder/decoder circuit |
| 04/07/1998 | US5737627 Pipelined data ordering system utilizing state machines to order data requests |
| 04/07/1998 | US5737604 Method and apparatus for independently resetting processors and cache controllers in multiple processor systems |
| 04/07/1998 | US5737603 Database system capable of carrying out an efficient free area search |
| 04/07/1998 | US5737599 Method and apparatus for downloading multi-page electronic documents with hint information |
| 04/07/1998 | US5737596 Sequential numerical information encoder and decoder |
| 04/07/1998 | US5737587 Resynchronization circuit for circuit module architecture |
| 04/07/1998 | US5737585 Firmware maintenance and modification system |
| 04/07/1998 | US5737575 Interleaved key memory with multi-page key cache |
| 04/07/1998 | US5737573 Asynchronous access system having an internal buffer control circuit which invalidates an internal buffer |
| 04/07/1998 | US5737572 Bank selection logic for memory controllers |
| 04/07/1998 | US5737571 System for discriminating that an external processor is permitted to access a data storage device utilizing prescribed control signals including access enable signal |
| 04/07/1998 | US5737569 Multiport high speed memory having contention arbitration capability without standby delay |
| 04/07/1998 | US5737568 Method and apparatus to control cache memory in multiprocessor system utilizing a shared memory |
| 04/07/1998 | US5737566 Data processing system having a memory with both a high speed operating mode and a low power operating mode and method therefor |
| 04/07/1998 | US5737565 System and method for diallocating stream from a stream buffer |
| 04/07/1998 | US5737564 Cache memory system having multiple caches with each cache mapped to a different area of main memory to avoid memory contention and to lessen the number of cache snoops |
| 04/07/1998 | US5737563 Determination of memory bank sizes in a computer system |
| 04/07/1998 | US5737550 Cache memory to processor bus interface and method thereof |
| 04/07/1998 | US5737523 In a distributed file system computing environment |
| 04/07/1998 | US5737509 Method and apparatus for restoring data coherency in a duplex shared memory subsystem |
| 04/07/1998 | US5737416 Method and apparatus for enabling trial period use of software products: method and apparatus for utilizing a decryption stub |
| 04/07/1998 | US5737258 Nonvolatile semiconductor memory which is connectable to a DRAM bus |
| 04/07/1998 | CA2120056C Desktop computer system having zero volt system suspend |
| 04/02/1998 | WO1998013763A2 Multiport cache memory with address conflict detection |