Patents for H03L 7 - Automatic control of frequency or phase; Synchronisation (37,643)
11/2005
11/16/2005EP1532737A4 Synchronous mirror delay (smd) circuit and method including a counter and reduced size bi-directional delay line
11/16/2005CN1698264A Delay lock loop circuit, and associated method, for a radio receiver
11/16/2005CN1697967A Measuring method, measuring signal output circuit, and measuring apparatus
11/16/2005CN1697325A Digital lock detector in use for phase locked loop
11/16/2005CN1697324A Method and device for redlization of debouncing for transmission signal
11/16/2005CN1696738A Signal processing circuit
11/16/2005CN1227856C Clock recovery circuit and receiver having clock recovery circuit
11/16/2005CN1227833C Multi-rate transponder system and chip set
11/16/2005CN1227815C Discriminator and lock phase ring using said discriminator
11/15/2005US6966022 System and method for determining integrated circuit logic speed
11/15/2005US6965761 Controlled oscillator circuitry for synthesizing high-frequency signals and associated method
11/15/2005US6965759 Frequency synthesizer capable of obtaining signals in three frequency bands
11/15/2005US6965660 Digital phase-locked loop
11/15/2005US6965273 Oscillator with improved parameters variation tolerance
11/15/2005US6965272 Worldwide marketing logistics network including strategically located centers for frequency programming crystal oscillators to customer specification
11/15/2005US6965271 Phase-locked loop
11/15/2005US6965259 Clock controlling method and circuit
11/15/2005US6965224 Method and apparatus for testing synchronization circuitry
11/10/2005WO2005107076A1 Circuits for use in radio communications
11/10/2005WO2005106888A1 Multiple data rate ram memory controller
11/10/2005US20050250464 Phase-lock loops
11/10/2005US20050249212 NCO based timebase recovery system and method for A/V decoder
11/10/2005US20050249028 Method and apparatus for generating a sequence of clock signals
11/10/2005US20050249027 Delay locked loop device
11/10/2005US20050248997 Semiconductor memory device for controlling output timing of data depending on frequency variation
11/10/2005US20050248901 Microcontroller with synchronised analog to digital converter
11/10/2005US20050248417 Controllable transient insertion device
11/10/2005US20050248413 Control signal generation for a low jitter switched-capacitor frequency synthesizer
11/10/2005US20050248412 Circuit for compensating charge leakage in a low pass filter capacitor of PLL systems
11/10/2005US20050248411 Phase-locked loop circuit
11/10/2005US20050248410 Injection-locked frequency divider and frequency dividing method thereof
11/10/2005US20050248395 High-speed switched-capacitor ripple-smoothing filter for low jitter phase-locked loop
11/10/2005US20050248394 Programmable/tunable active RC filter
11/10/2005US20050248380 System and method for generating multiple clock signals
11/10/2005US20050248377 Clock capture in clock synchronization circuitry
11/10/2005US20050248376 Circuit for compensating lpf capacitor charge leakage in phase locked loop systems
11/10/2005US20050248373 Frequency synthesizer with digital phase selection
11/10/2005DE4238374B4 Verfahren zur Erzeugung eines Signals mit einer steuerbaren stabilen Frequenz A method for generating a signal with a controllable stable frequency
11/10/2005DE102005008279A1 CDR-basierte Taktsynthese CDR-based clock synthesis
11/10/2005DE10157786B4 Verarbeitung von digitalen Hochgeschwindigkeitssignalen Processing of high-speed digital signals
11/10/2005CA2562752A1 Circuits for use in radio communications
11/09/2005EP1593199A2 Adaptive input logic for phase adjustments
11/09/2005EP1123580B1 Charge pump phase locked loop circuit
11/09/2005CN1695338A Techniques to adjust a signal sampling point
11/09/2005CN1695305A Synchronous mirror delay (SMD) circuit and method including a ring oscillator for timing coarse and fine delay intervals
11/09/2005CN1694360A Relay wire for signal adjustable in integrated circuit
11/09/2005CN1694359A General method of superwide band multifrequency point microwave signal
11/09/2005CN1694348A Symmetrical voltage controlled oscillator
11/09/2005CN1694347A Symmetrical voltage controlled oscillator
11/09/2005CN1694241A Method and circuit arrangement for resetting an integrated circuit
11/09/2005CN1694179A Delay locked loop device
11/09/2005CN1226827C Charge pump for lowering capacitance value needed by loop filter of phase locked loop
11/08/2005US6963629 Adaptive phase locked loop
11/08/2005US6963628 Multiphase retiming mechanism
11/08/2005US6963251 High noise rejection voltage-controlled ring oscillator architecture
11/08/2005US6963250 Voltage controlled oscillator with selectable frequency ranges
11/08/2005US6963249 Injection locking using direct digital tuning
11/08/2005US6963236 Method and apparatus for generating and controlling a quadrature clock
11/08/2005US6963235 Delay locked loop circuit with duty cycle correction function
11/08/2005US6963234 Phase regulating circuit with a time-delay element
11/08/2005US6963233 Charge pump phase locked loop with improved power supply rejection
11/08/2005US6963232 Compensator for leakage through loop filter capacitors in phase-locked loops
11/08/2005US6963110 System and method for ESD protection
11/03/2005WO2005104385A2 High agility frequency synthesizer phase-locked loop
11/03/2005WO2005045891A3 Method and apparatus for measuring and monitoring coatings
11/03/2005US20050246596 Auto-calibration method for delay circuit
11/03/2005US20050246141 Multiphase waveform generator capable of performing phase calibration and related phase calibration method
11/03/2005US20050245223 Method and arrangement for reducing phase jumps when switching between synchronisation sources
11/03/2005US20050245205 Signal enhancement device
11/03/2005US20050245200 Frequency multiplier pre-stage for fractional-N phase-locked loops
11/03/2005US20050243958 Clock recovery method for bursty communications
11/03/2005US20050243607 Data output controller in semiconductor memory device and control method thereof
11/03/2005US20050243163 Pixel clock generation circuit
11/03/2005US20050242898 Precision tunable voltage controlled oscillation and applications thereof
11/03/2005US20050242897 Method and apparatus for synthesizing high-frequency signals for wireless communications
11/03/2005US20050242894 Oscillator circuit
11/03/2005US20050242890 Adaptive frequency detector of phase locked loop
11/03/2005US20050242889 PLL modulation circuit and polar modulation apparatus
11/03/2005US20050242888 Phase-locked loop circuits with reduced lock time
11/03/2005US20050242872 Programmable/tunable active RC filter
11/03/2005US20050242871 Self calibration of continuous-time filters and systems comprising such filters
11/03/2005US20050242868 Supply tracking clock multiplier
11/03/2005US20050242865 Differential clock tree in an integrated circuit
11/03/2005US20050242864 Semiconductor device, semiconductor system, and digital delay circuit
11/03/2005US20050242860 FFT-based multichannel video receiver
11/03/2005US20050242859 Differential master/slave CML latch
11/03/2005US20050242857 Duty cycle correction
11/03/2005US20050242856 Interpolator circuit
11/03/2005US20050242855 Delay locked loop circuit
11/03/2005US20050242854 Delay locked loop circuit
11/03/2005US20050242853 Synchronous semiconductor memory device for reducing power consumption
11/03/2005US20050242852 Methods and apparatuses for detecting clock loss in a phase-locked loop
11/03/2005US20050242851 Signal generator with selectable mode control
11/03/2005US20050242850 Timing adjustment circuit and memory controller
11/03/2005US20050242848 Phase selectable divider circuit
11/03/2005US20050242843 Differential current mode phase/frequency detector circuit
11/03/2005US20050242842 Multi-function differential logic gate
11/03/2005US20050241196 Backhoe pivot joint
11/03/2005DE4498745B4 Funkfrequenztransceiver und Verfahren zum Betrieb desselben Same radio frequency transceiver and method of operation
11/03/2005DE102005017686A1 Phase-locked loop for communication between integrated circuit systems, has charge pump receiving control signals generated in response to comparison of reference clock signal and feedback signal