Patents
Sitemap › H03 - Basic electronic circuitry › H03L - Automatic control, starting, synchronisation, or stabilisation of generators of electronic oscillations or pulses › H03L 7 - Automatic control of frequency or phase; Synchronisation
Patents for H03L 7 - Automatic control of frequency or phase; Synchronisation (37,643)
11/2005
11/30/2005EP1599963A2 Clock and data recovery method and apparatus
11/30/2005EP1599943A2 Clock and data recovery phase-locked loop and high-speed phase detector architecture
11/30/2005EP1599942A1 Timing control circuit for an optical recording apparatus
11/30/2005EP1377839B1 Low-loss tunable ferro-electric device and method of characterization
11/30/2005EP1285498B1 High resolution phase frequency detectors
11/30/2005CN1703830A Method and device for generating a clock signal with predetermined clock signal properties
11/30/2005CN1702973A Digital delta sigma modulator and applications thereof
11/30/2005CN1702971A Digital tracking method of synchronous phase angle
11/30/2005CN1702970A Phase synchronous circuit
11/30/2005CN1702969A Delay chain immune to temperature virtually
11/30/2005CN1229780C Optical disc device and its producing method for clock signal and method for setting its optical quantum
11/30/2005CN1229706C Multiphase time clock generating circuit and time clock multiple circuit
11/29/2005US6970701 Radio calibration by correcting the crystal frequency
11/29/2005US6970683 PLL circuit and radio communication terminal apparatus using the same
11/29/2005US6970529 Unified digital architecture
11/29/2005US6970521 Circuit and system for extracting data
11/29/2005US6970055 Tunable planar capacitor
11/29/2005US6970047 Programmable lock detector and corrector
11/29/2005US6970046 Digital phase-locked loop
11/29/2005US6970045 Redundant clock module
11/29/2005US6970030 Dual phased-locked loop structure having configurable intermediate frequency and reduced susceptibility to interference
11/29/2005US6970029 Variable-delay signal generators and methods of operation therefor
11/29/2005US6970028 DLL circuit
11/29/2005US6970027 Apparatus for generating clock signal in optical disk and method thereof
11/29/2005US6969838 Image sensor
11/29/2005CA2279444C Double side band pilot technique for a control system that reduces distortion produced by electrical circuits
11/24/2005WO2005112266A1 Method and device for producing an oscillation with variable frequency
11/24/2005WO2005112265A1 Phase locked loop (pll) circuit, its phasing method and operation analyzing method
11/24/2005WO2005112260A1 Timing of ultra wideband pulse generator
11/24/2005US20050262373 DLL phase detection using advanced phase equal
11/24/2005US20050261797 Programmable radio transceiver
11/24/2005US20050259775 Dynamic phase alignment methods and apparatus
11/24/2005US20050258910 Voltage controlled oscillator
11/24/2005US20050258908 Digital phase locked loop with selectable normal or fast-locking capability
11/24/2005US20050258907 Phase-locked loops
11/24/2005US20050258906 Self-calibrating, fast-locking frequency synthesizer
11/24/2005US20050258901 System and method for linearizing a CMOS differential pair
11/24/2005US20050258883 Wide-range multi-phase clock generator
11/24/2005US20050258882 Interpolator circuit
11/24/2005US20050258881 Chip level clock tree deskew circuit
11/24/2005US20050258880 Internal reset signal generator for use in semiconductor memory
11/24/2005US20050258878 Frequency-dividing circuit arrangement and phase locked loop employing such circuit arrangement
11/24/2005US20050258770 Capacitive load driving circuit for driving capacitive loads such as pixels in plasma display panel, and plasma display apparatus
11/24/2005DE102005016299A1 Tastverhältniskorrektur Tastverhältniskorrektur
11/24/2005DE102004021398A1 Verfahren und Schaltungsanordnung zum Zurücksetzen einer integrierten Schaltung Method and circuit for resetting an integrated circuit
11/24/2005DE102004021224A1 Frequenzmultiplikatorvorstufe für gebrochen-N-phasenarretierte Schleifen Frequency multiplier precursor for fractional-N-phasenarretierte loops
11/23/2005EP1598939A1 Dynamic phase alignment methods and apparatus
11/23/2005EP1598802A2 Capacitive load driving circuit for driving capacitive loads such as pixels in a plasma display panel, and plasma display apparatus
11/23/2005EP1597827A1 Phase-locking circuit
11/23/2005EP1474872B1 Phase-locked-loop with reduced clock jitter
11/23/2005EP1076416B1 Phase-locked loop
11/23/2005CN1701512A VCO device
11/23/2005CN1701505A Modulator and correction method thereof
11/23/2005CN1700602A Dynamic phase alignment methods and apparatus
11/23/2005CN1700596A Circuit and method for generating level-triggered power up reset signal
11/23/2005CN1700590A Wideband signal generators, measurement devices, methods of signal generation, and methods of signal analysis
11/23/2005CN1700353A Memory device having delay locked loop
11/23/2005CN1228920C Dual-loop PLL
11/23/2005CN1228919C Ultra low jitter clock generation device and method for storage device and radio frequency system
11/23/2005CN1228918C Multiphase clock transfer circuit and method
11/23/2005CN1228916C Oscillator and electronic instrument using same
11/23/2005CN1228769C PLL circuit and data recording controller
11/22/2005US6968173 Tuner
11/22/2005US6968168 Variable oscillator
11/22/2005US6968027 Digital PLL device and digital PBX using the same
11/22/2005US6968026 Method and apparatus for output data synchronization with system clock in DDR
11/22/2005US6968025 High-speed transmission system having a low latency
11/22/2005US6968024 Apparatus and method for operating a master-slave system with a clock signal and a separate phase signal
11/22/2005US6968017 Low phase noise frequency converter
11/22/2005US6967539 Low phase-noise local oscillator and method
11/22/2005US6967538 PLL having VCO for dividing frequency
11/22/2005US6967536 Phase-locked loop circuit reducing steady state phase error
11/22/2005US6967513 Phase-locked loop filter with out of band rejection in low bandwidth mode
11/22/2005US6967512 Multiphase-clock processing circuit and clock multiplying circuit
11/22/2005US6967511 Method for synchronizing and resetting clock signals supplied to multiple programmable analog blocks
11/22/2005US6967503 Comparator
11/22/2005CA2240473C Digital frequency generator
11/22/2005CA2232758C Combining ntsc visual and aural signals with dtv signals
11/17/2005WO2005109733A1 Clock frequency reduction in communications receiver with coding
11/17/2005WO2005109732A2 Low power direct conversion rf transceiver architecture and asic and systems including such
11/17/2005WO2005109649A1 Clock capture in clock synchronization circuitry
11/17/2005WO2005109648A1 Method and apparatus for removing the otter on clock signal
11/17/2005WO2005109647A2 Adjustable frequency delay-locked loop
11/17/2005WO2005109643A1 Frequency synthesizer and method
11/17/2005WO2005109642A1 Equiphase polyphase clock signal generator circuit and serial digital data receiver circuit using the same
11/17/2005WO2005109148A1 Distributed loop components
11/17/2005US20050254318 Memory device having delay locked loop
11/17/2005US20050253658 Pll circuit
11/17/2005US20050253638 Method and circuit arrangement for resetting an integrated circuit
11/17/2005US20050253634 Linear charge pump for fractional synthesis using an auxiliary charge pump
11/17/2005US20050253633 PLL circuit and frequency setting circuit using the same
11/17/2005US20050253632 Low-power direct digital synthesizer with analog interpolation
11/17/2005US20050253631 Internal signal replication device and method
11/17/2005US20050253572 Delay locked loop circuit and method for testing the operability of the circuit
11/17/2005DE102005004860A1 Schaltung zum Erzeugen eines Spreizspektrumstaktes Circuit for generating a Spreizspektrumstaktes
11/17/2005DE102004020975A1 Oszillator und Verfahren zum Betreiben eines Oszillators Oscillator and method of operating an oscillator
11/17/2005DE102004019652A1 Fehlerkompensierte Ladungspumpen-Schaltung und Verfahren zur Erzeugung eines fehlerkompensierten Ausgangsstroms einer Ladungspumpen-Schaltung Error compensated charge pump circuit and method for generating an error-compensated output current of a charge pump circuit
11/16/2005EP1596219A1 Signal processing circuit for time delay determination
11/16/2005EP1595201A2 System and method for calibrating the clock frequency of a clock generator unit over a data line
11/16/2005EP1537668A4 Synchronous mirror delay (smd) circuit and method including a ring oscillator for timing coarse and fine delay intervals
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