Patents
Sitemap › H03 - Basic electronic circuitry › H03L - Automatic control, starting, synchronisation, or stabilisation of generators of electronic oscillations or pulses › H03L 7 - Automatic control of frequency or phase; Synchronisation
Patents for H03L 7 - Automatic control of frequency or phase; Synchronisation (37,643)
06/2005
06/30/2005US20050140407 System and method to improve the efficiency of synchronous mirror delays and delay locked loops
06/30/2005US20050140405 Power-up circuit semiconductor memory device
06/30/2005US20050140398 Clock switching circuit
06/30/2005DE10355187A1 Verfahren und Vorrichtung zur Timinganalyse einer Schaltung Method and device for timing analysis of a circuit
06/30/2005DE10354522A1 Verfahren und Schaltung zur Erzeugung einer Steuerspannung für einen spannungsgesteuerten Oszillator Method and circuit for generating a control voltage for a voltage controlled oscillator
06/30/2005CA2552394A1 Phase-locked loop
06/29/2005EP1548975A2 Burst communications apparatus and method using tapped delay lines
06/29/2005EP1548972A2 Transmitter device and relay device for performing data transmission control
06/29/2005EP1548945A1 DDS circuit with arbitrary frequency control clock
06/29/2005EP1547322A2 System for efficient recovery of node-b buffered data following mac layer reset
06/29/2005EP1547296A1 System and method for transferring data among transceivers substantially void of data dependent jitter
06/29/2005EP1547284A1 Techniques to reduce transmitted jitter in communication system
06/29/2005EP1547249A1 Voltage-controlled oscillator presetting circuit
06/29/2005EP1547238A2 Method of modulation gain calibration and system thereof
06/29/2005EP0968568B1 Emulating narrow band phase-locked loop behavior on a wide band phase-locked loop
06/29/2005CN1633745A Single point modulator having a PLL circuit
06/29/2005CN1633147A A method for implementing calling and called party pay intelligent service
06/29/2005CN1633028A Phase lock loop and loop filter therefor
06/29/2005CN1633027A A frequency and phase discriminator circuit with effective double frequency error-locking suppression
06/29/2005CN1633026A High-speed linear frequency modulation signal source
06/29/2005CN1632610A Universal digitized nuclear magnetic resonance frequency source
06/29/2005CN1208971C Predictive coding method and decoding method for dynamic image
06/29/2005CN1208961C Controlled oscillator in network of numerical symbol timing recovery
06/28/2005US6912666 Interleaved delay line for phase locked and delay locked loops
06/28/2005US6912380 PLL circuit and wireless mobile station with that PLL circuit
06/28/2005US6912260 System clock synchronization using phase-locked loop
06/28/2005US6912246 Clock signal transmitting system, digital signal transmitting system, clock signal transmitting method, and digital signal transmitting method
06/28/2005US6912012 Video decoder having lock algorithm that distinguishes between a noisy television signal input and a video recorder signal
06/28/2005US6911872 Circuit and method for generating a clock signal
06/28/2005US6911869 Voltage controlled oscillator capable of linear operation at very low frequencies
06/28/2005US6911868 Phase-locked loop frequency synthesizer using automatic loop control and method of operation
06/28/2005US6911853 Locked loop with dual rail regulation
06/28/2005US6911851 Data latch timing adjustment apparatus
06/28/2005US6911850 Semiconductor integrated circuit
06/28/2005US6911663 Transmission circuit and semiconductor device
06/28/2005CA2259360C Device and method for maintaining synchronization and frequency stability in a wireless telecommunication system
06/28/2005CA2222644C Frequency tracking for communication signals using m-ary orthogonal walsh modulation
06/23/2005WO2005057840A1 Clock data reproduction circuit
06/23/2005WO2005057793A1 Delta-sigma type fraction division pll synthesizer
06/23/2005WO2005057792A1 Phase-locked loop structures with enhanced signal stability
06/23/2005WO2005057791A1 High output impedance charge pump for pll/dll
06/23/2005WO2005057777A1 An oscillator circuit with tuneable signal delay means
06/23/2005WO2005057718A1 A delay-locked loop with precision controlled delay
06/23/2005WO2005031489A3 Current mirror compensation using channel length modulation
06/23/2005US20050138462 System and method for managing protocol network failures in a cluster system
06/23/2005US20050137816 Method for automatically calibrating the frequency range of a pll and associated pll capable of automatic calibration
06/23/2005US20050136873 Phase locked loop calibration
06/23/2005US20050135817 Control device with a switchable bandwidth
06/23/2005US20050135813 Linear full-rate phase detector and clock and data recovery circuit
06/23/2005US20050135529 Burst communications apparatus and method using tapped delay lines
06/23/2005US20050135526 Dual-PLL signaling for maintaining synchronization in a communications system
06/23/2005US20050135525 DDS circuit with arbitrary frequency control clock
06/23/2005US20050135523 Methods and arrangements for link power reduction
06/23/2005US20050135514 Synchronous clock generation apparatus and synchronous clock generation method
06/23/2005US20050135505 Frequency modulation circuit
06/23/2005US20050135471 Integrated decision feedback equalizer and clock and data recovery
06/23/2005US20050135470 Using clock and data recovery phase adjust to set loop delay of a decision feedback equalizer
06/23/2005US20050134491 Digital expander apparatus and method for generating multiple analog control signals particularly useful for controlling an oscillator
06/23/2005US20050134393 Oscillator with temperature control
06/23/2005US20050134392 Method and apparatus for reduced noise band switching circuits
06/23/2005US20050134391 Semiconductor integrated circuit having built-in PLL circuit
06/23/2005US20050134361 Adaptive body bias for clock skew compensation
06/23/2005US20050134351 Delay adjustment circuit, integrated circuit device, and delay adjustment method
06/23/2005US20050134339 Method and apparatus for data density-independent phase adjustment in a clock and data recovery system
06/23/2005US20050134337 Clock signal distribution with reduced parasitic loading effects
06/23/2005US20050134335 Phase-locked loop having a spread spectrum clock generator
06/23/2005US20050134334 Reset circuit
06/23/2005DE10354521A1 Verfahren zur Synchronisation mehrerer Oszillatoren Method for synchronization of multiple oscillators
06/23/2005CA2545983A1 An oscillator circuit with tuneable signal delay means
06/22/2005EP1545045A2 Integrated decision feedback equalizer and clock and data recovery
06/22/2005EP1545044A2 Decision feedback equalizer and clock and data recovery circuit for high-speed applications
06/22/2005EP1545043A2 Using clock and data recovery phase adjust to set loop delay of a decision feedback equalizer
06/22/2005EP1545028A2 Control device with variable bandwidth
06/22/2005EP1545008A1 PLL architecture
06/22/2005EP1545007A1 Local oscillator for harmonic image-rejection mixers
06/22/2005EP1545006A1 Local oscillator for harmonic image-rejection mixers
06/22/2005EP1543626A1 Method of and apparatus for reducing frequency errors associated with an inter-system scan
06/22/2005EP1543622A1 Waveform lineariser
06/22/2005EP1543621A1 Phase-locked loop
06/22/2005EP1543620A1 Phase locked loop
06/22/2005EP1543609A1 Voltage controlled lc tank oscillator
06/22/2005EP1212829B1 Method and apparatus for automatically compensating a spread spectrum clock generator
06/22/2005CN1630978A Digital phase locked loop
06/22/2005CN1630231A Weighted secret key sharing and reconstructing method
06/22/2005CN1630197A Method for automatically calibrating the frequency range of a PLL and associated PLL
06/22/2005CN1630196A Clock synchroniser
06/22/2005CN1630195A 调频电路 FM circuit
06/22/2005CN1630190A Delay adjustment circuit, integrated circuit device, and delay adjustment method
06/22/2005CN1629968A PLL circuit and an optical disk apparatus thereof
06/22/2005CN1207847C Phase-locked loop circuit
06/22/2005CN1207846C Different-frequency and same-source signal generator
06/22/2005CN1207845C PLL noise smoothing using dual-modulus interleaving
06/21/2005US6910144 Method and configuration for generating a clock pulse in a data processing system having a number of data channels
06/21/2005US6909852 Linear full-rate phase detector and clock and data recovery circuit
06/21/2005US6909762 Phase-locked loop circuit
06/21/2005US6909730 Phase-locked loop control of passively Q-switched lasers
06/21/2005US6909678 Method of consecutive writing on recordable disc
06/21/2005US6909344 Band switchable filter
06/21/2005US6909336 Discrete-time amplitude control of voltage-controlled oscillator
06/21/2005US6909332 System and method for tuning output drivers using voltage controlled oscillator capacitor settings
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