Patents for H03L 7 - Automatic control of frequency or phase; Synchronisation (37,643)
02/2006
02/01/2006EP1332592B1 Joint dc offset and channel estimation by using a least squares (ls) algorithm
02/01/2006CN1729528A Frequency and phase control apparatus and maximum likelihood decoder
02/01/2006CN1728830A Predictive coding device and decoding device for dynamic image
02/01/2006CN1728685A Method and system for facilitating data transfer in a pageable mode virtual environment
02/01/2006CN1728650A Method and arrangement for changing the operation mode of an agent of a management network
02/01/2006CN1728558A Circuits and methods for detecting phase lock
02/01/2006CN1728557A Method and device of generating clock signals
02/01/2006CN1728556A Circuit device and method of electronicregulator
02/01/2006CN1240192C Distribution of radio-frequency signals through low bandwidth infrastructure
01/2006
01/31/2006US6993314 Apparatus for generating multiple radio frequencies in communication circuitry and associated methods
01/31/2006US6993307 Method and apparatus for operating a PLL with a phase detector/sample hold circuit for synthesizing high-frequency signals for wireless communications
01/31/2006US6993306 Determination and processing for fractional-N programming values
01/31/2006US6993300 Accurate gain direct modulation (KMOD) using a dual-loop PLL
01/31/2006US6993109 Zero-delay buffer circuit for a spread spectrum clock system and method therefor
01/31/2006US6993107 Analog unidirectional serial link architecture
01/31/2006US6993104 Apparatus and method for adaptively adjusting a timing loop
01/31/2006US6993095 Phase-locked loop initialization via curve-fitting
01/31/2006US6992958 Phase-locked loop circuit for reproducing a channel clock
01/31/2006US6992950 Delay locked loop implementation in a synchronous dynamic random access memory
01/31/2006US6992536 Voltage-controlled oscillator
01/31/2006US6992531 Dual-oscillator signal synthesizer having high frequency offset stage
01/31/2006US6992514 Synchronous mirror delay circuit and semiconductor integrated circuit device having the same
01/26/2006US20060017847 Video synchronization by adjusting video parameters
01/26/2006US20060017519 Low-latency start-up for a monolithic clock generator and timing/frequency reference
01/26/2006US20060017518 Method and apparatus for reducing the start time of a vcxo
01/26/2006US20060017512 Circuit for detecting phase errors and generating control signals and PLL using the same
01/26/2006US20060017511 Phase locked loop comprising a sigma-delta modulator
01/26/2006US20060017510 Semiconductor integrated circuit
01/26/2006US20060017498 Digital phase locked loop
01/26/2006US20060017484 Timing vernier using a delay locked loop
01/26/2006US20060017480 Method and apparatus to set a tuning range for an analog delay
01/26/2006US20060017479 Method and apparatus for digital phase generation at high frequencies
01/26/2006US20060017478 Delay-locked loop with feedback compensation
01/26/2006US20060017477 Systems and methods for initializing plls and measuring vco characteristics
01/26/2006US20060017476 Phase locked loop integrated circuits having fast locking characteristics and methods of operating same
01/26/2006US20060017475 PLL output clock stabilization circuit
01/26/2006DE29825196U1 Schaltung zum Einstellen einer Taktverzögerung Circuit for adjusting a clock delay
01/26/2006DE19806097B4 Gerät zum Senden von Hochfrequenzsignalen Device for transmitting high-frequency signals
01/26/2006DE10217852B4 Verfahren und Vorrichtung zur Ansteuerung eines Oszillators oder einer Phasenverzögerungseinrichtung in einem Phasenregelkreis Method and apparatus for controlling an oscillator or a phase delay device in a phase locked loop
01/26/2006DE102004030841A1 Verringerung der Einschwingzeit und Kompensation von Phasenfeldern von auf Phasenregelkreisen basierenden Frequenzsynthesizern Reduction of settling time and compensation of phase fields of frequency synthesizers based on phase-locked loops
01/25/2006EP1619819A1 Clock data recovery circuit
01/25/2006EP1619790A1 Direct digital frequency synthesis enabling spur elimination
01/25/2006EP1618461A1 Deskew system in a clock distribution network using a pll and a dll
01/25/2006CN1726643A Low lock time delay locked loops using time cycle supppressor
01/25/2006CN1726642A Coarse delay tuner circuits with edge suppressors in delay locked loops
01/25/2006CN1725645A Quick frequency conversion integral phase-lock frequency synthesizer
01/25/2006CN1725644A Synchronous phase changing device of camera synchronous locked
01/25/2006CN1725643A Synchronous signal transformation device of black-white camera synchronous locked
01/25/2006CN1725636A Circuit for tuning conduction capacity time constant
01/25/2006CN1725629A Low frequency clock signal generating method and low frequency cloc ksignal generator
01/25/2006CN1238971C Clock restoring circuit phase discriminator design method and structure for realising same
01/24/2006US6990644 On chip timing adjustment in multi-channel fast data transfer
01/24/2006US6990597 Clock generation circuit, data transfer control device, and electronic instrument
01/24/2006US6990165 Phase and frequency lock detector
01/24/2006US6990164 Dual steered frequency synthesizer
01/24/2006US6990163 Apparatus and method for acquiring phase lock timing recovery in a partial response maximum likelihood (PRML) channel
01/24/2006US6990154 Using an IF synthesizer to provide raster component of frequency channel spacing
01/24/2006US6990143 50% duty-cycle clock generator
01/24/2006US6990122 Synchronism phase-switching circuit for the recovery of received data
01/24/2006US6989718 Circuit and method for phase locked loop charge pump biasing
01/24/2006US6989700 Delay locked loop in semiconductor memory device and its clock locking method
01/24/2006US6989699 Phase detection circuit having a substantially linear characteristic curve
01/24/2006US6989698 Charge pump circuit for compensating mismatch of output currents
01/24/2006US6989697 Non-quasistatic phase lock loop frequency divider circuit
01/24/2006US6989696 System and method for synchronizing divide-by counters
01/24/2006US6989695 Apparatus and method for reducing power consumption by a data synchronizer
01/19/2006US20060014513 Communication semiconductor integrated circuit device and a wireless communication system
01/19/2006US20060013345 Oscillator frequency control
01/19/2006US20060012712 Locking display pixel clock to input frame rate
01/19/2006US20060012447 Amplitude control circuit
01/19/2006US20060012443 Oscillator circuit for a sensor
01/19/2006US20060012442 Semiconductor integrated circuit with PLL circuit
01/19/2006US20060012441 Phase-locked loop with conditioned charge pump output
01/19/2006US20060012440 Phase locked loop
01/19/2006US20060012439 Linear phase detector and charge pump
01/19/2006US20060012438 Phase locked loop with nonlinear phase-error response characteristic
01/19/2006US20060012410 Measure-controlled delay circuits with reduced phase error
01/19/2006US20060012409 Power on reset circuit
01/19/2006DE102005027559A1 Verfahren zur Verringerung der Fraktionalstörung und ein Fraktional-N-PLL-Oszillator, der die Fraktionalstörung verringert A method for reducing the Fraktionalstörung and a fractional-N-PLL oscillator which reduces the Fraktionalstörung
01/19/2006DE10130122B4 Verzögerungsregelkreis Delay locked loop
01/19/2006DE10111402B4 Verfahren und Phasenregelkreis zur Synchronisation auf einen in einem Nutzsignal enthaltenen Hilfsträger The method and phase-locked loop for synchronization with a subcarrier contained in a useful signal
01/18/2006EP1617563A1 Integrated circuit including crystal oscillator emulator
01/18/2006EP1617561A2 System and Method for Producing Precision Timing Signals
01/18/2006EP1616389A1 Device for detecting the temperature of an oscillator crystal
01/18/2006CN1722839A Video encoding and decoding methods and video encoder and decoder
01/18/2006CN1722734A A method for automatic configuration of terminal equipment
01/18/2006CN1722655A Cdr-based clock synthesis
01/18/2006CN1721965A Integrated circuit including processor and crystal oscillator emulator
01/18/2006CN1237719C Phase-locked loop circuit and method for eliminating self-shaking in signals received by control circuit
01/17/2006US6987701 Phase detector for all-digital phase locked and delay locked loops
01/17/2006US6987423 Two port voltage controlled oscillator for use in wireless personal area network synthesizers
01/17/2006US6987410 Clock recovery circuit and communication device
01/17/2006US6987409 Analog delay locked loop with tracking analog-digital converter
01/17/2006US6987408 Digital delay locked loop and control method thereof
01/17/2006US6987407 Delay locked loops having delay time compensation and methods for compensating for delay time of the delay locked loops
01/17/2006US6987406 Wide frequency range phase-locked loop circuit with phase difference
01/17/2006US6987405 Apparatus and method for generating multi-phase signals with digitally controlled trim capacitors
01/17/2006US6987404 Synchronizer apparatus for synchronizing data from one clock domain to another clock domain
01/12/2006WO2006004893A1 Phase error cancellation
01/12/2006WO2006002844A1 Apparatus comprising a sigma-delta modulator and method of generating a quantized signal in a sigma-delta modulator