Patents for H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof (658,974) |
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05/06/1992 | EP0483517A2 Gas delivery for ion beam deposition and etching |
05/06/1992 | EP0483487A1 Self-aligned epitaxial base transistor and method for fabricating same |
05/06/1992 | EP0483365A1 Silicon single crystal manufacturing apparatus |
05/06/1992 | EP0483349A1 Method for control of photoresist develop processes |
05/06/1992 | EP0483319A1 Etching indium tin oxide |
05/06/1992 | EP0256053B1 Matrix of interconnected transistors in thin layers and production method thereof |
05/06/1992 | CN1060923A Production method for rectifier diode |
05/06/1992 | CN1060861A Enhancement of polyimide adhesion on reactive metals |
05/06/1992 | CN1060830A Chemically stabilized cristobalite |
05/05/1992 | US5111491 X-ray lithography mask and method for producing same |
05/05/1992 | US5111435 Bipolar-CMOS semiconductor memory device |
05/05/1992 | US5111434 Semiconductor memory device |
05/05/1992 | US5111404 Method for managing production line processes |
05/05/1992 | US5111355 Thin films, high capacitance |
05/05/1992 | US5111279 Apparatus for isolation of flux materials in "flip-chip" manufacturing |
05/05/1992 | US5111276 Thick bus metallization interconnect structure to reduce bus area |
05/05/1992 | US5111275 Multicell semiconductor memory device |
05/05/1992 | US5111272 Semiconductor device having element regions electrically isolated from each other |
05/05/1992 | US5111271 Semiconductor device using standard cell system |
05/05/1992 | US5111270 Three-dimensional contactless non-volatile memory cell |
05/05/1992 | US5111269 Bipolar transistor structure containing a resistor which assures reduction in layout area |
05/05/1992 | US5111267 Semiconductor device having a multilayer electrode structure and method for fabricating the same |
05/05/1992 | US5111265 Collector-top type transistor causing no deterioration in current gain |
05/05/1992 | US5111261 Silicon thin film transistor with an intrinsic silicon active layer formed within the boundary defined by the edges of the gate electrode and the impurity containing silicon layer |
05/05/1992 | US5111259 Trench capacitor memory cell with curved capacitors |
05/05/1992 | US5111258 Semiconductor device with a multi-stepped source region and method for producing the same |
05/05/1992 | US5111257 Electronic integrated circuit having an electrode layer for element isolation |
05/05/1992 | US5111256 High speed semiconductor device and an optelectronic device |
05/05/1992 | US5111255 Buried channel heterojunction field effect transistor |
05/05/1992 | US5111240 Method for forming a photoresist pattern and apparatus applicable therewith |
05/05/1992 | US5111068 Diffusion resistor circuit |
05/05/1992 | US5111063 Integrated clock driver circuit |
05/05/1992 | US5110766 Method of manufacturing a semiconductor device including forming a flattening layer over hollows in a contact hole |
05/05/1992 | US5110765 Selective etch for GaAs-containing group III-V compounds |
05/05/1992 | US5110764 Method of making a beveled semiconductor silicon wafer |
05/05/1992 | US5110763 Glass coating |
05/05/1992 | US5110762 Manufacturing a wiring formed inside a semiconductor device |
05/05/1992 | US5110761 Formed top contact for non-flat semiconductor devices |
05/05/1992 | US5110760 Vertical, vapor deposition of metal |
05/05/1992 | US5110759 Melting |
05/05/1992 | US5110758 Method of heat augmented resistor trimming |
05/05/1992 | US5110757 Formation of composite monosilicon/polysilicon layer using reduced-temperature two-step silicon deposition |
05/05/1992 | US5110756 Method of semiconductor integrated circuit manufacturing which includes processing for reducing defect density |
05/05/1992 | US5110755 Process for forming a component insulator on a silicon substrate |
05/05/1992 | US5110754 Method of making a DRAM capacitor for use as an programmable antifuse for redundancy repair/options on a DRAM |
05/05/1992 | US5110752 Metal silicides |
05/05/1992 | US5110751 Etching, vapor deposition of gate metal |
05/05/1992 | US5110750 Semiconductor device and method of making the same |
05/05/1992 | US5110749 Method for manufacturing semiconductor device |
05/05/1992 | US5110748 Glass, silicon |
05/05/1992 | US5110712 High density multi-level interconnects |
05/05/1992 | US5110709 Light-sensitive positive working composition containing a pisolfone compound |
05/05/1992 | US5110708 Positives |
05/05/1992 | US5110706 I-line radiation-sensitive alkali-soluble resin composition utilizing 1,2-quinone diazide compound and hydroxy-chalcone additive |
05/05/1992 | US5110697 Multifunctional photolithographic compositions |
05/05/1992 | US5110654 Ceramic multilayer wiring substrate |
05/05/1992 | US5110628 Without touching its leads |
05/05/1992 | US5110515 Method of encapsulating semiconductor chips |
05/05/1992 | US5110438 Reduced pressure surface treatment apparatus |
05/05/1992 | US5110437 Plasma processing apparatus |
05/05/1992 | US5110428 Differently polarizing front and rear surfaces |
05/05/1992 | US5110411 Method of isotropically dry etching a poly/WSix sandwich structure |
05/05/1992 | US5110410 Etching thick resist coating back to zinc sulfide and then etching both until all of resist is removed |
05/05/1992 | US5110409 Enhanced plasma etching |
05/05/1992 | US5110408 Anisotropic etching of gate film with good accuracy |
05/05/1992 | US5110407 Surface fabricating device |
05/05/1992 | US5110404 High temperature followed by low temperature of oxygen |
05/05/1992 | US5110394 Apparatus for forming interconnection pattern |
05/05/1992 | US5110388 Method of dicing and bonding semiconductor chips using a photocurable and heat curable adhesive tape |
05/05/1992 | US5110373 Layer having non-uniform dopant concentration |
05/05/1992 | US5110299 High density interconnect |
05/05/1992 | US5110249 Transport system for inline vacuum processing |
05/05/1992 | US5110248 Vertical heat-treatment apparatus having a wafer transfer mechanism |
05/05/1992 | US5110167 Disc handling device, method of use and package |
05/05/1992 | US5110032 Method and apparatus for wire bonding |
05/05/1992 | US5110001 Handle for wafer carrier |
05/05/1992 | US5109981 Carrier and carrier system for flatpack integrated circuits |
05/05/1992 | US5109980 Ic carrier with shaft coupling |
05/05/1992 | US5109601 Method of marking a thin film package |
05/05/1992 | CA1300282C Wire bonds and electrical contacts of an integrated circuit device |
05/05/1992 | CA1300281C Substrate potential detecting circuit |
05/05/1992 | CA1299983C Passivation of gallium arsenide surfaces |
05/05/1992 | CA1299982C Passivation of gallium arsenide electron devices |
05/02/1992 | CA2053492A1 Device fabrication and resulting devices |
05/01/1992 | CA2185936A1 Process for fabricating a superconducting circuit |
04/30/1992 | WO1992007384A1 Piso electrostatic discharge protection device |
04/30/1992 | WO1992007383A1 Semiconductor device |
04/30/1992 | WO1992007382A1 Structure of semiconductor device and manufacturing method thereof |
04/30/1992 | WO1992007380A1 Semiconductor device having switching circuit to be switched by light and its fabrication process |
04/30/1992 | WO1992007379A1 Dual-mode z-stage |
04/30/1992 | WO1992007378A1 Process for producing a hybrid semiconductor structure and semiconductor structure thus produced |
04/30/1992 | WO1992007377A1 Sacrificial metal etchback system |
04/30/1992 | WO1992007376A1 Semiconductor processing apparatus and method |
04/30/1992 | WO1992007362A1 Semiconductor memory unit having redundant structure |
04/30/1992 | DE4134172A1 Tape automated bonding interconnect device mfr. |
04/30/1992 | DE4116696A1 Opto=electronic integrated circuit mfr. - by depositing mask layer on substrate surface and forming mask for selective growth |
04/30/1992 | DE4033658A1 Processing trench edges in semiconductor substrates - using stream of particles, for simple, accurate silicon@ solar cell mfr. |
04/30/1992 | CA2054164A1 Transport device for the transfer of a workpiece carrier |
04/29/1992 | EP0482940A1 Method of forming an electrical connection for an integrated circuit |
04/29/1992 | EP0482907A2 Electrode structures |