Patents
Patents for G06F 13 - Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units (158,002)
03/1984
03/15/1984WO1984001078A1 Four way selector switch for a five port module as a node in an asynchronous speed independent network of concurrent processors
03/14/1984EP0102434A1 Device to signal to the central control unit of a data processing equipment the errors occurring in the adapters
03/13/1984US4437168 Communication control unit
03/13/1984US4437158 In a computer system
03/13/1984US4437157 Dynamic subchannel allocation
03/13/1984CA1163722A1 Shared peripheral processing system
03/13/1984CA1163690A1 Supervisory control of peripheral subsystems
03/07/1984EP0102278A1 Universal coupling device for the intercommunication of information processing systems and at least one peripheral unit
03/06/1984US4435762 Machine-implemented method
03/06/1984US4435761 Data processing apparatus capable of transferring serial data with small power consumption
03/06/1984US4435755 Method in a data processing system
03/06/1984US4435754 Method of selecting PROM data for selective mapping system
03/06/1984US4435732 Electro-optical illumination control system
03/06/1984CA1163342A1 Communication subsystem with an automatic abort upon transmit underrun
02/1984
02/28/1984US4434466 Apparatus for controlling the access of processors at a data line
02/28/1984US4434463 Multiprocessor topology with plural bases for directly and indirectly coupling addresses and relay stations
02/28/1984US4434460 Hierarchical computer system for generating selective output signals in response to received input signals
02/22/1984EP0101377A1 Device for the control of the transfer of files between computers
02/21/1984US4433391 Digital system
02/21/1984US4433379 Microcomputer system with input/output unit connected to the remainder of the system by a single multibit bus and several sequential data lines
02/21/1984US4433376 Intersystem translation logic system
02/21/1984CA1162655A1 Memory protection system using capability registers
02/21/1984CA1162654A1 Binary input processing in a digital computer
02/15/1984EP0100712A1 System for the detection of programmable stop codes in a data transfer between a local microprocessor memory and a peripheral unit in a processor system using a direct access circuit to a local memory
02/15/1984EP0100655A2 Data flow control system
02/15/1984EP0100594A2 Improved local area network systems
02/15/1984EP0100460A2 Request selection control in a processor-memory connection system
02/14/1984US4432055 Memory subsystem for use in a system
02/14/1984US4432054 Loop data transmission control method and system
02/14/1984US4432053 Address generating apparatus and method
02/14/1984CA1162316A1 Bus access control circuitive
02/14/1984CA1162315A1 Message protocol module
02/14/1984CA1162314A1 Data input/output method and system
02/08/1984EP0100240A2 System creation method and apparatus
02/08/1984EP0100092A2 Multiple communication interface between processor and digital transmission means
02/07/1984US4430710 In a data communications network
02/07/1984US4430702 Network access device
02/07/1984US4430700 System and method for communication between nodes of a closed loop local communication path
02/07/1984US4430699 Distributed data processing system
02/07/1984US4430651 Expandable and contractible local area network system
02/02/1984WO1984000426A1 Database management system for controlling concurrent access to a database
02/01/1984EP0099462A2 Apparatus and method for buffering data in a data processing system
02/01/1984EP0099407A1 Digital system including line activity detection.
02/01/1984EP0099404A1 Text comparator.
01/1984
01/31/1984US4429384 Communication system having an information bus and circuits therefor
01/31/1984US4429382 Microprocessor multiplexer method and apparatus for bisynchronous data
01/31/1984US4429362 Data buffer operating in response to computer halt signal
01/24/1984US4428048 Data processing system
01/24/1984US4428046 Data processing system having a star coupler with contention circuitry
01/24/1984US4428044 Peripheral unit controller
01/24/1984US4428043 Data communications network
01/24/1984US4428042 Interface device for coupling a system of time-division multiplexed channels to a data concentrator
01/24/1984CA1161136A1 Communication link contention resolution system
01/19/1984WO1984000222A1 I/o channel bus
01/19/1984WO1984000220A1 Programmable priority arbitration system
01/19/1984WO1984000219A1 I/o bus clock
01/19/1984WO1984000215A1 Scaling of sound source signatures in underwater seismic exploration
01/18/1984EP0098494A2 Asynchronous bus multiprocessor system
01/17/1984US4426681 Process and device for managing the conflicts raised by multiple access to same cache memory of a digital data processing system having plural processors, each having a cache memory
01/17/1984US4426679 Communication multiplexer using a random access memory for storing an acknowledge response to an input/output command from a central processor
01/17/1984CA1160712A1 Arbitration controller providing for access of a common resource by a duplex plurality of central processing units
01/17/1984CA1160711A1 Multi-master station, multi-channel digital communication system with channel selection provided at each terminal
01/11/1984EP0098260A2 Circuit arrangement for controlling the synchronous transmission of data
01/11/1984EP0098259A2 Circuit arrangement for controlling the quasi-synchronous transmission of data
01/11/1984EP0098170A2 Access control processing system in computer system
01/11/1984EP0097977A2 Frequency synthesizer
01/11/1984EP0097834A2 Circuits for accessing a variable width data bus with a variable width data field
01/10/1984US4425664 Multiport programmable digital data set
01/10/1984US4425625 Diagnostic display terminal system
01/10/1984US4425616 High-speed time share processor
01/10/1984CA1160351A1 Virtual memory terminal
01/10/1984CA1160312A1 Microprocessor based computer terminal
01/04/1984EP0097499A2 Access request control apparatus for a data processing system
01/04/1984EP0097351A2 Router unit and routing network for determining an output port by detecting a part of an input packet
01/03/1984US4424565 Channel interface circuit with high speed data message header field translation and direct memory access
12/1983
12/28/1983EP0097028A2 Multiple-microcomputer communications system
12/27/1983US4423480 Buffered peripheral system with priority queue and preparation for signal transfer in overlapped operations
12/27/1983CA1159574A1 Data processing system including internal register addressing arrangements
12/27/1983CA1159563A1 Electronic postage meter having plural computing systems
12/22/1983WO1983004464A1 Automatic calling unit control system
12/22/1983WO1983004440A1 Read write system for multiple line adapter organization
12/21/1983EP0096578A2 Automatic calling unit control system
12/21/1983EP0096577A2 Read write system for multiple line adapter organization
12/21/1983EP0096456A2 Capstanless magnetic tape drive with electronic equivalent to length of tape
12/21/1983EP0096407A1 Universal computer-printer interface
12/21/1983EP0096113A2 Bus system
12/20/1983US4422148 Electronic postage meter having plural computing systems
12/20/1983US4422142 System for controlling a plurality of microprocessors
12/20/1983CA1159155A1 Sequential word aligned address apparatus
12/20/1983CA1159127A1 Apparatus and method for data interface to an input/output multiplexer from multiple control interface units
12/13/1983US4420831 Method and device for frequency translation
12/13/1983US4420806 Interrupt coupling and monitoring system
12/13/1983US4420695 Synchronous priority circuit
12/13/1983CA1158780A1 Storage addressing control apparatus
12/13/1983CA1158779A1 Multi-processor system
12/13/1983CA1158778A1 Dynamic device address assignment mechanism for a data processing system
12/13/1983CA1158775A1 Computer annotation system
12/13/1983CA1158741A1 Bi-directional information transfer on a single direction bus
12/13/1983CA1158740A1 Terminal providing communication system information output
12/13/1983CA1158737A1 Shared synchronous memory multiprocessing arrangement