Patents
Patents for H01L 29 - Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. pn-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof (218,143)
02/2015
02/24/2015US8962426 Method of manufacture for a semiconductor device
02/24/2015US8962422 Method of fabricating semiconductor devices
02/24/2015US8962421 Methods for fabricating integrated circuits including semiconductive resistor structures in a FinFET architecture
02/24/2015US8962419 Complementary stress memorization technique layer method
02/24/2015US8962418 Manufacturing method of semiconductor device having semiconductor layers with different thicknesses
02/24/2015US8962417 Method and structure for pFET junction profile with SiGe channel
02/24/2015US8962416 Split gate non-volatile memory cell
02/24/2015US8962415 Methods of forming gates of semiconductor devices
02/24/2015US8962414 Reduced spacer thickness in semiconductor device fabrication
02/24/2015US8962412 Integrated circuit having raised source drains devices with reduced silicide contact resistance and methods to fabricate same
02/24/2015US8962409 Semiconductor device and fabrication method
02/24/2015US8962408 Replacement gate self-aligned carbon nanostructure transistor
02/24/2015US8962406 Flatband shift for improved transistor performance
02/24/2015US8962405 Method of manufacturing semiconductor device by mounting and positioning a semiconductor die using detection marks
02/24/2015US8962403 Manufacturing method for switch and array substrate using etching solution comprising amine
02/24/2015US8962402 Lateral diffusion metal oxide semiconductor (LDMOS) device with tapered drift electrode
02/24/2015US8962401 Double gated 4F2 dram CHC cell and methods of fabricating the same
02/24/2015US8962400 In-situ doping of arsenic for source and drain epitaxy
02/24/2015US8962399 Method of making a semiconductor layer having at least two different thicknesses
02/24/2015US8962398 Body contacted hybrid surface semiconductor-on-insulator devices
02/24/2015US8962397 Multiple well drain engineering for HV MOS devices
02/24/2015US8962386 Semiconductor device and method for manufacturing the same
02/24/2015US8962369 Method for doping semiconductor structures and the semiconductor device thereof
02/24/2015US8962354 Methods for forming templated materials
02/24/2015US8962348 Co/Ni multilayers with improved out-of-plane anisotropy for magnetic device applications
02/24/2015US8962137 Branched nanowire and method for fabrication of the same
02/24/2015US8961815 Composition for advanced node front-and back-end of line chemical mechanical polishing
02/24/2015US8961814 High-selectivity wet patterning of source-drain electrodes over TAOS for a BCE device structure
02/24/2015US8961687 Lattice matched crystalline substrates for cubic nitride semiconductor growth
02/24/2015US8961685 Method of manufacturing silicon single crystal, silicon single crystal, and wafer
02/24/2015US8960970 Light emitting device and method for manufacturing same
02/19/2015WO2015023760A1 Methods of fabricating silicon nanowires and devices containing silicon nanowires
02/19/2015WO2015023521A1 Embedded micro valve in microphone
02/19/2015WO2015023349A1 Edge termination technique for high voltage power devices
02/19/2015WO2015022989A1 Semiconductor device
02/19/2015WO2015022777A1 Tunnel field-effect transistor, method for manufacturing same, and switch element
02/19/2015WO2015022744A1 Method for manufacturing semiconductor device having sgt
02/19/2015WO2015021944A1 Lateral double diffused metal oxide semiconductor field-effect transistor
02/19/2015WO2015021927A1 Laterally double-diffused metal-oxide-semiconductor field effect transistor
02/19/2015US20150050817 Method of preventing voltage breakdown at a surface of a semiconductor substrate of a superjunction semiconductor device
02/19/2015US20150050803 Methods of forming semiconductor devices, including forming patterns by performing an oxidation process
02/19/2015US20150050800 Fin formation by epitaxial deposition
02/19/2015US20150050793 Semiconductor device and method of fabricating the same
02/19/2015US20150050792 Extra narrow diffusion break for 3d finfet technologies
02/19/2015US20150050791 Method for manufacturing rectifier with vertical mos structure
02/19/2015US20150050790 Semiconductor device and method of manufacturing the same
02/19/2015US20150050788 Current steering element formation for memory arrays
02/19/2015US20150050787 Fully silicided gate formed according to the gate-first hkmg approach
02/19/2015US20150050784 Bi-directional silicon controlled rectifier structure
02/19/2015US20150050776 Sputtering target, method for manufacturing the same, and method for manufacturing semiconductor device
02/19/2015US20150050775 Method for manufacturing semiconductor device
02/19/2015US20150050774 Semiconductor device and method for manufacturing the semiconductor device
02/19/2015US20150050471 Method for producing iii-n templates and the reprocessing thereof and iii-n template
02/19/2015US20150049557 Non-volatile memory device and operation and fabricating methods thereof
02/19/2015US20150049277 Semiconductor device and method of manufacturing the semiconductor device
02/19/2015US20150048884 Amplifier circuits
02/19/2015US20150048489 Edge termination technique for high voltage power devices
02/19/2015US20150048487 Plasma polymerized thin film having high hardness and low dielectric constant and manufacturing method thereof
02/19/2015US20150048486 Spatial semiconductor structure and method of fabricating the same
02/19/2015US20150048485 Methods of forming films including germanium tin and structures and devices including the films
02/19/2015US20150048478 Trench isolation for bipolar junction transistors in bicmos technology
02/19/2015US20150048477 Semiconductor structure and manufacturing method thereof
02/19/2015US20150048476 Semiconductor devices and methods of manufacture
02/19/2015US20150048475 Semiconductor Structures With Shallow Trench Isolations
02/19/2015US20150048460 Gate structure for semiconductor device
02/19/2015US20150048459 Device for detecting a laser attack in an integrated circuit chip
02/19/2015US20150048456 Metal gate features of semiconductor die
02/19/2015US20150048455 Self-aligned gate contact structure
02/19/2015US20150048454 Method for fabricating a gate all around device
02/19/2015US20150048453 FinFETs and Methods for Forming the Same
02/19/2015US20150048452 Ultra-high voltage semiconductor having an isolated structure for high side operation and method of manufacture
02/19/2015US20150048451 Semiconductor device and manufacturing method for the same
02/19/2015US20150048450 Semiconductor device and method for manufacturing semiconductor device
02/19/2015US20150048449 High Voltage Semiconductor Device and Method of Forming the Same
02/19/2015US20150048448 Semiconductor device and method for forming the same
02/19/2015US20150048447 Lateral diffusion metal oxide semiconductor (ldmos) device with tapered drift electrode
02/19/2015US20150048446 Reduction of oxide recesses for gate height control
02/19/2015US20150048445 Semiconductor Chip with Integrated Series Resistances
02/19/2015US20150048444 Semiconductor devices including bit line contact plug and peripheral transistor
02/19/2015US20150048443 Semiconductor device
02/19/2015US20150048442 Semiconductor arrangement with one or more semiconductor columns
02/19/2015US20150048441 Semiconductor arrangement with one or more semiconductor columns
02/19/2015US20150048440 Nonvolatile semiconductor memory device and method of manufacturing the same
02/19/2015US20150048439 Split gate embedded memory technology and method of manufacturing thereof
02/19/2015US20150048438 Nonvolatile semiconductor memory device
02/19/2015US20150048437 Semiconductor memory device and method for manufacturing the same
02/19/2015US20150048436 Nonvolatile semiconductor memory device and production method for the same
02/19/2015US20150048434 Structure and Method of Manufacturing a Stacked Memory Array for Junction-Free Cell Transistors
02/19/2015US20150048432 Meander Line Resistor Structure
02/19/2015US20150048431 Method for forming a contact on a semiconductor substrate and semiconductor device
02/19/2015US20150048430 Sidewall image transfer with a spin-on hardmask
02/19/2015US20150048429 Sidewall image transfer with a spin-on hardmask
02/19/2015US20150048428 Method of manufacturing a semiconductor device using source/drain epitaxial overgrowth for forming self-aligned contacts without spacer loss and a semiconductor device formed by same
02/19/2015US20150048423 Semiconductor device having a iii-v crystalline compound material selectively grown on the bottom of a space formed in a single element substrate.
02/19/2015US20150048422 A method for forming a crystalline compound iii-v material on a single element substrate
02/19/2015US20150048421 High electron mobility transistors, methods of manufacturing the same, and electronic devices including the same
02/19/2015US20150048420 Integrated Circuit with First and Second Switching Devices, Half Bridge Circuit and Method of Manufacturing
02/19/2015US20150048419 Semiconductor device and method of manufacturing the same
02/19/2015US20150048418 Semiconductor power device
02/19/2015US20150048417 Germanium Barrier Embedded in MOS Devices
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 ... 2182