Patents
Patents for G11C 7 - Arrangements for writing information into, or reading information out from, a digital store (53,197)
05/2013
05/01/2013CN101720484B Multi-level cell access buffer with dual function
05/01/2013CN101479804B High-performance flash memory data transfer
04/2013
04/30/2013US8433023 Method and apparatus for generating a phase dependent control signal
04/30/2013US8432763 Integrated circuit
04/30/2013US8432762 Bitline sense amplifier, memory core including the same and method of sensing charge from a memory cell
04/30/2013US8432761 Data bus control scheme for and image sensor and image sensor including the same
04/30/2013US8432759 Measuring electrical resistance
04/30/2013US8432757 Semiconductor system and method for operating the same
04/30/2013US8432756 Collision prevention in a dual port memory
04/30/2013US8432755 Random access memory devices having word line drivers therein that support variable-frequency clock signals
04/30/2013US8432754 Memory control apparatus and mask timing adjusting method
04/30/2013US8432753 High speed interface for multi-level memory
04/30/2013US8432752 Adaptive write procedures for non-volatile memory using verify read
04/30/2013US8432751 Memory cell using BTI effects in high-k metal gate MOS
04/30/2013US8432750 Non-volatile memory systems and methods including page read and/or configuration features
04/30/2013US8432748 Semiconductor memory device capable of memorizing multivalued data
04/30/2013US8432747 Static random access memory (SRAM) and test method of the SRAM having precharge circuit to prepcharge bit line
04/30/2013US8432746 Memory page buffer
04/30/2013US8432386 Switch device for source driver of liquid crystal display and operating method thereof
04/25/2013WO2013059808A1 System and method for mram having controlled averagable and isolatable voltage reference
04/25/2013WO2013058743A1 Bit cell write-assistance
04/25/2013WO2013057532A1 Memory device and method for organizing a homogeneous memory
04/25/2013US20130104004 Ram memory device
04/25/2013US20130103898 Driver for ddr2/3 memory interfaces
04/25/2013US20130100755 Semiconductor memory device implementing comprehensive partial array self refresh scheme
04/25/2013US20130100754 Non-volatile semiconductor memory device and method of reading data thereof
04/25/2013US20130100753 Data transmission circuit and semiconductor apparatus using the same
04/25/2013US20130100751 Precharge signal generation circuit, semiconductor device including the same, and method for generating precharge signal
04/25/2013US20130100750 Semiconductor device
04/25/2013US20130100749 Nano-sense amplifier
04/25/2013US20130100748 Semiconductor memory device and method for driving the same
04/25/2013US20130100747 Semiconductor memory device and method of operating the same
04/25/2013US20130100746 Methods and apparatus of stacking drams
04/25/2013US20130100730 Method and apparatus for word line suppression
04/25/2013US20130100727 Overwriting a memory array
04/25/2013US20130100726 Multi-level memory cell with continuously tunable switching
04/25/2013DE102012219059A1 Effizientes Befehlsabbildungsschema für Kurze-Datenburstlängen- Speichervorrichtungen Efficient instruction mapping scheme for short-Datenburstlängen- storage devices
04/24/2013EP2583280A2 Balanced on-die termination
04/24/2013CN202907181U 多功能智能扩音器 Multifunctional smart microphone
04/24/2013CN202905186U Bus card with music player
04/24/2013CN202905185U Recordable note board
04/24/2013CN202905184U MP4 device with improved structure
04/24/2013CN202905183U Novel electronic player
04/24/2013CN202905182U Double-interface U disk
04/24/2013CN202905181U Memorizer capable of being used as USB (Universal Serial Bus) cable
04/24/2013CN202905180U USB flash disk
04/24/2013CN202905179U Multifunctional USB (Universal Serial Bus) flash disc
04/24/2013CN202905178U Data storage circuit for single phase watt hour meter
04/24/2013CN202904499U Storage mouse
04/24/2013CN202896748U Electric bike with audio playing and function of voltage detection
04/24/2013CN202896033U Universal serial bus (USB) flash disk pen
04/24/2013CN103065671A Method and system for adaptively adjusting working voltage of chips
04/24/2013CN103065670A Dual-port memorizer and manufacturing method thereof
04/24/2013CN103065669A 自动音乐播放电路 Automatic music playback circuit
04/24/2013CN103065668A Memory and reading method thereof
04/24/2013CN103065667A Memory device and negative bit line signal generating device thereof
04/24/2013CN103065666A Connection type U disk
04/24/2013CN101853214B Storage device
04/24/2013CN101777375B Method for matching induction amplifier
04/24/2013CN101740109B Bit line cutting high-performance buffer
04/24/2013CN101572117B Semiconductor memory device and method for operating the same
04/24/2013CN101461008B Non-volatile semiconductor memory with page erase
04/23/2013US8429741 Altered token sandboxing
04/23/2013US8427899 Self-adaptive sensing design
04/23/2013US8427897 Memory with output control
04/23/2013US8427896 Dynamic wordline assist scheme to improve performance tradeoff in SRAM
04/23/2013US8427895 Systems, memories, and methods for repair in open digit memory architectures
04/23/2013US8427892 Write strobe generation for a memory interface controller
04/23/2013US8427891 Hybrid volatile and non-volatile memory device with a shared interface circuit
04/23/2013US8427890 Program cycle skip
04/23/2013US8427889 Memory device and associated main word line and word line driving circuit
04/23/2013US8427888 Word-line driver using level shifter at local control circuit
04/23/2013US8427886 Memory device with trimmable power gating capabilities
04/23/2013US8427885 Nonvolatile semiconductor memory device
04/23/2013US8427884 Bit scan circuits and method in non-volatile memory
04/23/2013US8427883 Setting circuit and integrated circuit including the same
04/23/2013US8427882 Voltage signals multiplexer
04/23/2013US8427861 Semiconductor memory device
04/23/2013US8427683 Information processing apparatus, control method, and storage medium
04/23/2013CA2414920C A high speed dram architecture with uniform access latency
04/18/2013WO2013055332A1 Select device for cross point memory structures
04/18/2013WO2013028434A3 Memory device readout using multiple sense times
04/18/2013WO2013028430A3 Memory device with reduced sense time readout
04/18/2013US20130097395 Method and apparatus for sending data from multiple sources over a communications bus
04/18/2013US20130094314 Sram power reduction through selective programming
04/18/2013US20130094313 Collision prevention in a dual port memory
04/18/2013US20130094312 Voltage scaling device of semiconductor memory
04/18/2013US20130094311 Dynamic phase shifter and staticizer
04/18/2013US20130094310 Methods and apparatus for synchronizing communication with a memory controller
04/18/2013US20130094309 Tracking bit cell
04/18/2013US20130094307 Bit line voltage bias for low power memory design
04/18/2013US20130094306 Integrated circuit comprising a non-dedicated terminal for receiving an erase program high voltage
04/18/2013US20130094305 Device for supplying a high erase program voltage to an integrated circuit
04/18/2013US20130094304 Nonvolatile memory device
04/18/2013US20130094303 Complementary Reference Method for High Reliability Trap-Type Non-Volatile Memory
04/18/2013US20130094302 Integrated circuit chip and semiconductor memory device
04/18/2013US20130094301 Interfaces and die packages, and appartuses including the same
04/18/2013US20130094300 Reading devices for memory arrays
04/18/2013US20130094298 Storage devices with soft processing
04/18/2013US20130094276 Apparatuses and methods for determining stability of a memory cell
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