Patents
Patents for G11C 7 - Arrangements for writing information into, or reading information out from, a digital store (53,197)
10/1995
10/10/1995US5457661 Semiconductor memory device having a delay circuit for controlling access time
10/10/1995US5457659 Programmable dynamic random access memory (DRAM)
10/10/1995US5457657 High-speed sense amplifier having feedback loop
10/10/1995US5457654 Memory circuit for pre-loading a serial pipeline
10/10/1995US5457648 Random access memory with digital signals running over the small signal region of the array
10/10/1995US5457647 Passive hierarchical bitline memory architecture which resides in metal layers of a SRAM array
10/04/1995EP0675500A1 An improved memory device and method of construction
10/03/1995US5455803 Semiconductor device which operates at a frequency controlled by an external clock signal
10/03/1995US5455802 Dual dynamic sense amplifiers for a memory array
10/03/1995US5455795 Semiconductor memory device
09/1995
09/28/1995WO1995022802A3 Method of converting a series of m-bit information words to a modulated signal, method of producing a record carrier, coding device, decoding device, recording device, reading device, signal, as well as a record carrier
09/27/1995EP0674411A1 Virtual interconnection memory especially for communication between terminals operating at different speeds
09/27/1995EP0674318A1 System and method for write-protecting predetermined portions of a memory array
09/27/1995EP0674317A2 A reference potential generator and a semiconductor memory device having the same
09/26/1995US5453957 Memory architecture for burst mode access
09/26/1995US5453956 Load generator used in semiconductor memory device
09/26/1995US5453955 Non-volatile semiconductor memory device
09/26/1995US5453951 Fast voltage equilibration of complementary data lines following write cycle in memory circuits
09/20/1995EP0673137A1 Virtual interconnection memory
09/20/1995EP0673036A2 Semiconductor memory device having split transfer function
09/20/1995EP0525068A4 Integrated circuit i/o using a high preformance bus interface
09/19/1995US5452261 Serial address generator for burst memory
09/19/1995US5452259 Multiport memory with pipelined serial input
09/19/1995US5452255 Semiconductor memory device
09/19/1995US5452254 Semiconductor memory device
09/19/1995US5452251 Semiconductor memory device for selecting and deselecting blocks of word lines
09/19/1995US5452249 Non-volatile semiconductor memory device with verify mode for verifying data written to memory cells
09/14/1995DE19502598A1 CMOS input buffer with n=type and p=type MOSFETs
09/13/1995EP0671814A2 Delay locked loop for detecting the phase difference of two signals having different frequencies
09/13/1995EP0671744A2 Synchronous memory having parallel output data paths
09/13/1995EP0555417B1 Register forwarding multi-port register file
09/12/1995US5450566 Register block circuit for central processing unit of microcomputer
09/12/1995US5450367 Memory device
09/12/1995US5450366 IC memory card
09/12/1995US5450361 Semiconductor memory device having redundant memory cells
09/12/1995US5450356 Programmable pull-up buffer
09/12/1995US5450355 Multi-port memory device
09/12/1995US5450353 Static random access memory device having reset controller
09/08/1995WO1995024040A1 Memory core organization
09/07/1995DE19507562A1 Semiconductor memory device, esp. synchronous video RAM
09/05/1995US5448717 Transparently inserting wait states into memory accesses when microprocessor in performing in-circuit emulation
09/05/1995US5448714 Sequential-access and random-access dual-port memory buffer
09/05/1995US5448528 Synchronous DRAM having initial mode setting circuit
09/05/1995US5448524 Semiconductor memory device
08/1995
08/31/1995DE4413823A1 Data block access mechanism for memory chip devices
08/30/1995EP0669620A2 Multiplexer
08/29/1995US5446879 Disc changing apparatus with error logging
08/24/1995WO1995022802A2 Method of converting a series of m-bit information words to a modulated signal, method of producing a record carrier, coding device, decoding device, recording device, reading device, signal, as well as a record carrier
08/23/1995EP0668592A1 Internal timing method and circuit for programmable memories
08/23/1995EP0668591A1 Read timing method and circuit for nonvolatile memories
08/23/1995EP0668557A1 Data reorganization circuit
08/22/1995US5444666 Data output equipment for a semiconductor memory device
08/22/1995US5444665 Semiconductor memory device
08/22/1995US5444656 Apparatus for fast internal reference cell trimming
08/22/1995US5444654 ROM with Bi-CMOS gate arrays
08/22/1995US5444652 Semiconductor memory device having a memory cell unit including a plurality of transistors connected in series
08/22/1995US5444398 Decoded-source sense amplifier with special column select driver voltage
08/22/1995US5444305 Semiconductor memory circuit
08/17/1995DE19503390A1 Datenausgabepuffer-Steuerschaltung Data output buffer control circuit
08/16/1995EP0667622A2 Electronic still camera
08/16/1995EP0667621A2 Semiconductor memory device
08/16/1995EP0667620A2 Semiconductor memory device
08/15/1995US5442308 Dynamic decoder circuit operative at low frequency clock signals without data destruction
08/10/1995DE4439775A1 Bus interface circuit for FIFO
08/10/1995DE19503964A1 Semiconductor memory with data output buffer
08/10/1995DE19503596A1 DRAM Semiconductor memory operated by external clock pulse signal
08/09/1995EP0665979A1 Verifiable security circuitry for preventing unauthorized access to programmed read only memory.
08/08/1995US5440718 Single semiconductor substrate RAM device utilizing data compressing/expanding mechanism in a multi-microprocessor environment
08/08/1995US5440684 Parallel to serial conversion of information data
08/08/1995US5440522 Connection/disconnection control circuit for data lines between memory groups
08/08/1995US5440517 DRAMs having on-chip row copy circuits for use in testing and video imaging and method for operating same
08/08/1995US5440515 Delay locked loop for detecting the phase difference of two signals having different frequencies
08/08/1995US5440514 Write control for a memory using a delay locked loop
08/08/1995US5440512 Semiconductor memory device
08/08/1995US5440506 Semiconductor ROM device and method
08/08/1995US5440148 Quantum operational device
08/02/1995EP0665557A2 Semiconductor memory device
08/02/1995EP0665556A2 Semiconductor memory device
08/02/1995EP0665555A2 Semiconductor memory device
08/02/1995EP0226616B1 Asynchronous row and column control
08/01/1995US5438551 Semiconductor integrated circuit device
08/01/1995US5438548 Synchronous memory with reduced power access mode
08/01/1995US5438547 Memory-unit sense amplifier
08/01/1995US5438287 High speed differential current sense amplifier with positive feedback
07/1995
07/26/1995EP0664614A1 Decoder circuit which resists a fluctuation of a power supply
07/25/1995US5436871 Optical random access memory having folded image
07/25/1995US5436870 Semiconductor memory device
07/25/1995US5436869 Memory controller which can carry out a high speed access when supplied with input addresses with a time interval left between the input addresses having the same row address
07/25/1995US5436866 Low-power, high-speed sense amplifier
07/25/1995US5436865 Output circuit for semiconductor memory device realizing extended data output upon inactivation of CAS signal
07/25/1995US5436864 Semiconductor memory device having an improved data transmission circuit
07/25/1995US5436862 IC card including multiple connectors providing memory write production
07/19/1995EP0663665A2 Memory cell with programmable antifuse technology
07/18/1995US5434969 Video display system using memory with a register arranged to present an entire pixel at once to the display
07/18/1995US5434823 Output signal driver
07/18/1995US5434822 Apparatus and method for adjusting and maintaining a bitline precharge level
07/18/1995US5434821 Dynamic semiconductor memory device having sense amplifier with compensated offset voltage
07/12/1995EP0662689A2 Semiconductor memory device
07/12/1995EP0662663A2 Semiconductor memory with built-in cache
07/12/1995EP0662659A1 Method for minimizing the effect of memory errors within a digital information storage system