Patents
Sitemap › G11 - Information storage › G11C - Static stores › G11C 5 - Details of stores covered by group
Patents for G11C 5 - Details of stores covered by group (20,391)
12/2013
12/03/2013US8599595 Memory devices with serially connected signals for stacked arrangements
12/03/2013US8598944 Semiconductor integrated circuit deciding a power-supply voltage based on a delay test
11/2013
11/28/2013US20130318293 Semiconductor memory device, and method of controlling the same
11/28/2013US20130315021 Semiconductor device and method for driving semiconductor device
11/28/2013US20130315020 Semiconductor memory device, and method of controlling the same
11/28/2013US20130315012 Semiconductor memory device, and method of controlling the same
11/28/2013US20130315010 Period signal generation circuits
11/28/2013US20130315009 Period signal generation circuit
11/28/2013US20130315008 Period signal generation circuit
11/28/2013US20130314991 Semiconductor device
11/28/2013US20130314969 Nonvolatile semiconductor memory device
11/28/2013US20130314968 Offsetting clock package pins in a clamshell topology to improve signal integrity
11/28/2013US20130314967 Memory having buried digit lines and methods of making the same
11/28/2013DE102008053535B4 Schaltung eines Regelkreises Circuit of a control loop
11/26/2013US8593890 Implementing supply and source write assist for SRAM arrays
11/26/2013US8593888 Semiconductor memory device
11/26/2013US8593887 Semiconductor device having reference voltage generating unit
11/26/2013US8593874 Voltage generation circuit which is capable of reducing circuit area
11/26/2013US8593859 Semiconductor device for preventing erroneous write to memory cell in switching operational mode between normal mode and standby mode
11/26/2013US8593849 Memory device interface methods, apparatus, and systems
11/26/2013US8593848 Programming method for programming flash memory array structure
11/26/2013US8593847 Stacked semiconductor devices including a master device
11/26/2013CA2495759C Method and system of external data storage
11/21/2013WO2013173042A1 Memory chip power management
11/21/2013US20130308409 Integrated circuit device, power management module and method for providing power management
11/21/2013US20130308407 Controlling a voltage level of an access signal to reduce access disturbs in semiconductor memories
11/21/2013US20130308406 Semiconductor device, method for operating the same, and memory system including the same
11/21/2013US20130308396 Driver for semiconductor memory and method thereof
11/21/2013US20130308363 Three dimensional non-volatile storage with interleaved vertical select devices above and below vertical bit lines
11/20/2013CN103403803A Memory system in which extended function can easily be set
11/20/2013CN102113056B Dual power scheme in memory circuit
11/20/2013CN101040343B Word line driver circuit for a static random access memory and method therefor
11/19/2013US8588011 Semiconductor device and method
11/19/2013US8588008 Interleaving charge pumps for programmable memories
11/19/2013US8587991 Recycling charges
11/19/2013US8587982 Non-volatile memory array configurable for high performance and high density
11/19/2013US8587981 Memory, computing system and method for checkpointing
11/14/2013WO2013169235A1 Adaptive voltage input to a charge pump
11/14/2013WO2013071254A3 Circuit and method for generating a reference level for a magnetic random access memory element
11/14/2013US20130301373 Memory Chip Power Management
11/14/2013US20130301372 Memory device, memory system, and power management method
11/14/2013US20130301365 Dedicated reference voltage generation circuit for memory
11/14/2013US20130301364 Sense amplifier ciruit and semiconductor device
11/14/2013US20130301361 Row driver architecture
11/14/2013US20130301332 Semiconductor device
11/14/2013US20130301331 Semiconductor device and driving method of semiconductor device
11/14/2013US20130301330 Semiconductor device having hierarchical bit line structure
11/14/2013DE19956550B4 Trimmschaltung für systemintegrierte Schaltung Trimming circuit for system integrated circuit
11/13/2013CN101719974B Digital broadcast transmitter
11/12/2013US8582388 Serial advanced technology attachment dual in-line memory module (SATA DIMM) capable of preventing data loss
11/12/2013US8582387 Method and apparatus for supplying power to a static random access memory (SRAM) cell
11/12/2013US8582386 Internal voltage generator and semiconductor memory device including the same
11/12/2013US8582385 Semiconductor memory device
11/12/2013US8582374 Method and apparatus for dynamically adjusting voltage reference to optimize an I/O system
11/12/2013US8582348 Semiconductor device and method for driving semiconductor device
11/12/2013US8582341 Semiconductor device and method for manufacturing same
11/12/2013US8582340 Word line and power conductor within a metal layer of a memory cell
11/12/2013US8582339 System including memory stacks
11/07/2013WO2013043269A3 Combination of mutually used high power supplemental charge pump with signal level individual low power charge pumps to supply word lines in a non-volatile memory
11/07/2013WO2013043268A3 High voltage charge pump regulation system with decoupled large and fine step|adjustment
11/07/2013US20130297890 Memory system having a plurality of types of memory chips and a memory controller for controlling the memory chips
11/07/2013US20130297862 Memory system having a plurality of types of memory chips and a memory controller for controlling the memory chips
11/07/2013US20130297861 Memory system having a plurality of types of memory chips and a memory controller for controlling the memory chips
11/07/2013US20130297860 Memory system having a plurality of types of memory chips and a memory controller for controlling the memory chips
11/07/2013US20130294149 Reducing power in sram using supply voltage control
11/07/2013US20130294146 Resistive memory device and method of fabricating the same
11/07/2013US20130294137 Semiconductor device having bit line hierarchically structured
11/07/2013US20130294136 Global bit line pre-charge circuit that compensates for process, operating voltage, and temperature variations
11/07/2013US20130294135 Semiconductor device having hierarchically structured bit lines and system including the same
11/07/2013US20130294134 Stacked layer type semiconductor device and semiconductor system including the same
11/07/2013US20130294133 Semiconductor device
11/07/2013US20130294132 Memory Arrays
11/07/2013US20130293285 Booster Circuit, Semiconductor Device and Electronic Apparatus
11/06/2013CN103383860A Resistive memory device and method of fabricating the same
11/06/2013CN102044285B Memory power supply circuit
11/06/2013CN101919002B Stackable storage system and manufacture method thereof
11/05/2013US8578244 Programming error correction code into a solid state memory device with varying bits per cell
11/05/2013US8576651 Temperature compensation of conductive bridge memory arrays
11/05/2013US8576599 Multi-wafer 3D CAM cell
11/05/2013US8575697 SRAM-type memory cell
11/05/2013US8574992 Contact architecture for 3D memory array
10/2013
10/31/2013WO2013111371A3 Flash nand memory device with stacked blocks and common wordlines
10/31/2013WO2013052372A3 Stub minimization for multi-die wirebond assemblies with parallel windows
10/31/2013WO2013052324A3 Stub minimization using duplicate sets of signal terminals in assemblies without wirebonds to package substrate
10/31/2013US20130286761 Switching circuit
10/31/2013US20130286708 Memory edge cell
10/31/2013US20130286707 Stub minimization using duplicate sets of signal terminals
10/31/2013US20130286706 Memory Modules and Devices Supporting Configurable Data Widths
10/30/2013EP2656346A2 Memory array having local source lines
10/30/2013CN103377685A Apparatus for SRAM cells
10/30/2013CN103377684A Semiconductor memory device and writing method of ID codes and upper addresses
10/29/2013US8570816 Digital memory system that dynamically adjusts reference voltage as a function of traffic intensity
10/29/2013US8570815 Semiconductor device and method of controlling the same
10/24/2013WO2013158557A1 Erase operation for 3d non volatile memory with controllable gate-induced drain leakage current
10/24/2013WO2013158556A1 Soft erase operation for 3d non-volatile memory with selective inhibiting of passed bits
10/24/2013WO2013158242A2 Permanent solid state memory using carbon-based or metallic fuses
10/24/2013US20130279241 Circuits and methods for reducing minimum supply for register file cells
10/24/2013US20130279233 Vertical non-volatile memory device and method of fabricating the same
10/24/2013US20130279232 Apparatus, system, and method for transferring heat from memory components
10/23/2013CN103366789A Memory array with hierarchical bit line structure
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