Patents
Sitemap › G11 - Information storage › G11C - Static stores › G11C 5 - Details of stores covered by group
Patents for G11C 5 - Details of stores covered by group (20,391)
11/2005
11/03/2005US20050243591 Apparatus and methods for optically-coupled memory systems
11/03/2005US20050243590 Apparatus and methods for optically-coupled memory systems
11/03/2005US20050243589 Apparatus and methods for optically-coupled memory systems
11/03/2005US20050242829 Circuit module
11/03/2005US20050242794 Voltage regulator
11/03/2005US20050242441 Improved metal wiring pattern for memory devices
11/03/2005US20050242375 Very fine-grain voltage island integrated circuit
11/03/2005DE102005017686A1 Phase-locked loop for communication between integrated circuit systems, has charge pump receiving control signals generated in response to comparison of reference clock signal and feedback signal
11/03/2005DE102005015595A1 Mehrchipgehäuse mit Taktfrequenzeinstellung Multi-chip package with clock frequency setting
11/03/2005DE102004015890A1 Memory system for e.g. laptop computer, has set of volatile memory modules and one nonvolatile memory module that stores identifiers, which indicate assignment of volatile memory modules` characteristics in set of volatile memory modules
11/03/2005DE102004015269A1 Integrierte Schaltung Integrated circuit
11/02/2005EP1591858A1 Trimming functional parameters in integrated circuits
11/02/2005CN1691482A Constant-current generating circuit
11/02/2005CN1691201A Write line design in MRAM and its manufacturing method
11/02/2005CN1691197A Memory with low and fixed pre-charge loading
11/02/2005CN1691196A Memory device including self-ID information
11/02/2005CN1691061A Data storage device and control apparatus, data storage control method, and program
11/01/2005US6961831 Techniques for increasing bandwidth in port-per-module memory systems having mismatched memory modules
11/01/2005US6961281 Single rank memory module for use in a two-rank memory module system
11/01/2005US6961271 Memory device in which memory cells having complementary data are arranged
11/01/2005US6961270 Power-up circuit in semiconductor memory device
11/01/2005US6961269 Memory device having data paths with multiple speeds
11/01/2005US6961265 Magnetic non-volatile memory coil layout architecture and process integration scheme
11/01/2005US6961260 Semiconductor storage circuit and layout method for the same
11/01/2005US6961259 Apparatus and methods for optically-coupled memory systems
11/01/2005US6960495 Method for making contacts in a high-density memory
10/2005
10/27/2005WO2005101418A2 State retention within a data processing system
10/27/2005US20050241005 Data processing apparatus and method for operating a dual rail circuit component
10/27/2005US20050240714 System and method for virtual content repository deployment
10/27/2005US20050237844 Method and apparatus for controlled persistent ID flag for RFID applications
10/27/2005US20050237843 Method and apparatus for controlled persistent ID flag for RFID applications
10/27/2005US20050237825 Data processing apparatus
10/27/2005US20050237824 Semiconductor memory device including floating gates and control gates, control method for the same, and memory card including the same
10/27/2005US20050237823 Dynamically adaptable memory
10/27/2005US20050237822 Resynchronization circuit
10/27/2005US20050237821 Method and system of external data storage
10/27/2005US20050237820 Semiconductor integrated circuit device
10/27/2005US20050237819 Data output apparatus for memory device
10/27/2005US20050237791 Solid-state memory device and method for arrangement of solid-state memory cells
10/27/2005US20050237778 System with meshed power and signal buses on cell array
10/27/2005US20050237106 Constant-current generating circuit
10/27/2005US20050237105 Self-biased bandgap reference voltage generation circuit insensitive to change of power supply voltage
10/27/2005US20050237103 Area efficient charge pump
10/27/2005US20050237102 Semiconductor integrated circuit device
10/27/2005US20050237101 Charge pump clock for non-volatile memories
10/27/2005US20050237039 Semiconductior device and memory card using same
10/27/2005US20050235809 Server apparatus streaming musical composition data matching performance skill of user
10/27/2005DE102005006131A1 Load adjustment circuit for non-volatile memory array e.g. erasable programmable ROM, has control unit enabled to decrease power supplied to load if power supplied to load is greater than maximum threshold
10/26/2005CN2736888Y 硬盘驱动器 Hard Drive
10/26/2005CN1689159A Semiconductor integrated circuit device and method for controlling semiconductor integrated circuit device
10/26/2005CN1689111A Software refreshed memory device and method
10/26/2005CN1225025C Semiconductor memory
10/25/2005US6958947 Semiconductor memory device with internal voltage generators for testing a memory array and peripheral circuits
10/20/2005WO2005096796A2 Method and apparatus for a dual power supply to embedded non-volatile memory
10/20/2005US20050235093 Apparatus and method for managing registers in a processor to emulate a portion of stack
10/20/2005US20050234659 Write line design in MRAM
10/20/2005US20050232098 Method for track jump control
10/20/2005US20050232068 Semiconductor memory device
10/20/2005US20050232065 Method and circuit for controlling operation mode of PSRAM
10/20/2005US20050232062 Apparatus and methods for optically-coupled memory systems
10/20/2005US20050232059 Semiconductor device with non-volatile memory and random access memory
10/20/2005US20050232054 Semiconductor device
10/20/2005US20050232053 Semiconductor integrated circuit device
10/20/2005US20050232052 Apparatus and method for supplying power in semiconductor device
10/20/2005US20050232034 Auxiliary device for operating M-DOC series flash memory and non-X86 system processor in synchronism
10/20/2005US20050232029 Write pulse generation for recording on optical media
10/20/2005US20050232027 Data storage device, data storage control apparatus, data storage control method, and data storage control program
10/20/2005US20050232026 Ultraviolet erasable semiconductor memory device
10/20/2005US20050232023 Method and apparatus for selecting memory cells within a memory array
10/20/2005US20050231991 Semiconductor device having a power down mode
10/20/2005US20050231985 Voltage up converter
10/20/2005US20050231271 Internal supply voltage generator for delay locked loop circuit
10/20/2005US20050231269 Device for controlling the operation of internal voltage generator
10/20/2005US20050231246 Power-up detector
10/20/2005US20050231123 Semiconductor device
10/19/2005EP1587112A2 Buffered memory module with configurable interface width.
10/19/2005EP1587080A1 Method for track jump control
10/19/2005CN1685437A System for controlling mode changes in a voltage down-converter
10/19/2005CN1685436A Data memory
10/19/2005CN1684199A Internal voltage generation circuit of semiconductor memory device
10/19/2005CN1684195A High voltage generating circuit preserving charge pumping efficiency
10/19/2005CN1684159A Method for track jump control
10/18/2005US6957158 High density random access memory in an intelligent electric device
10/18/2005US6956509 Method, system, and apparatus for remote data calibration of a RFID tag population
10/18/2005US6956261 Semiconductor device and method for manufacturing the same
10/18/2005US6955967 Non-volatile memory having a reference transistor and method for forming
10/13/2005WO2005096311A1 Enhanced mechanical acoustic sound generation system and method
10/13/2005WO2005094405A2 Closed loop dynamic power management
10/13/2005WO2005094325A2 Systems and methods for gathering data concerning usage of media data
10/13/2005WO2005078606A3 Clustered hierarchical file services
10/13/2005WO2005074611A8 Interrupt management for multiple event queues
10/13/2005US20050228939 System and method for optimizing interconnections of components in a multichip memory module
10/13/2005US20050228936 Method and apparatus for managing context switches using a context switch history table
10/13/2005US20050228929 Bridge circuit
10/13/2005US20050228612 Multichip package with clock frequency adjustment
10/13/2005US20050226090 Pseudo SRAM having combined synchronous and asynchronous mode register set
10/13/2005US20050226089 Memory chip architecture having non-rectangular memory banks and method for arranging memory banks
10/13/2005US20050226080 Memory module and impedance calibration method of semiconductor memory device
10/13/2005US20050226077 Static memory cell having independent data holding voltage
10/13/2005US20050226076 Method for increasing stability of system memory through enhanced quality of supply power
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