Patents
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Patents for G11C 5 - Details of stores covered by group (20,391)
12/2005
12/15/2005US20050276146 Semiconductor memory device
12/15/2005US20050276134 Memory device
12/15/2005US20050276127 Semiconductor integrated circuit device having power supply startup sequence
12/15/2005US20050276126 Programmable impedance control circuit in semiconductor device and impedance range shifting method thereof
12/15/2005US20050276123 Addressing type serial/parallel data transmitting system
12/15/2005US20050276110 Nonvolatile memory apparatus
12/15/2005US20050276088 Liquid crystal display device and method for driving the same
12/15/2005US20050275986 Method and device for controlling internal power voltage, and semiconductor memory device having the same
12/15/2005US20050275977 Multi-level power supply system for a complementary metal oxide semiconductor circuit
12/15/2005US20050275674 General serial interface system
12/15/2005DE4207226B4 Integrierte Schaltung Integrated circuit
12/15/2005DE202005011287U1 Memory e.g. flash memory, card for e.g. portable computer, has chip modules, which are arranged on switching card with disk, and grooves that are formed along cut area to enable direct cutting of edges and corners of card
12/14/2005EP1605354A1 Method and apparatus for improved synchronization of a processing unit for multimedia streams in a multithreaded environment
12/14/2005CN1707801A Semiconductor storage device
12/14/2005CN1707773A Standard cell, semiconductor integrated circuit device of standard cell scheme and layout design method for semiconductor integrated circuit device
12/14/2005CN1707696A Memory device
12/14/2005CN1707691A Semiconductor integrated circuit device having power supply startup sequence
12/14/2005CN1707690A Semiconductor memory device having a global data bus
12/14/2005CN1707435A Method and apparatus for processing data in a processing unit being a thread in a multithreading environment
12/13/2005US6976120 Apparatus and method to track flag transitions for DRAM data transfer
12/13/2005US6975558 Integrated circuit device
12/13/2005US6975553 Nonaligned access to random access memory
12/13/2005US6975552 Hybrid open and folded digit line architecture
12/13/2005US6975535 Electronic memory, such as flash EPROM, with bitwise-adjusted writing current or/and voltage
12/13/2005US6975527 Memory device layout
12/13/2005US6975164 Method and device for generating constant voltage
12/13/2005US6975158 Noise canceling circuit
12/08/2005WO2005117019A1 Dram interface circuits having enhanced skew, slew rate and impedence control
12/08/2005WO2005116917A1 Semiconductor memory card
12/08/2005WO2005116838A1 Configurable width buffered module having a bypass circuit
12/08/2005WO2005116800A2 Throttling memory in a computer system
12/08/2005WO2005116720A1 Mems device having time-varying control
12/08/2005US20050270891 Backwards-compatible memory module
12/08/2005US20050270890 Circuit and method for detecting frequency of clock signal and latency signal generation circuit of semiconductor memory device with the circuit
12/08/2005US20050270889 Dynamic random access memory (DRAM) capable of canceling out complimentary noise development in plate electrodes of memory cell capacitors
12/08/2005US20050270882 High voltage generators having an integrated discharge path for use in non-volatile semiconductor memory devices
12/08/2005US20050270880 Internal power management scheme for a memory chip in deep power down mode
12/08/2005US20050270875 Hierarchical module
12/08/2005US20050270868 Semiconductor memory device and method for adjusting internal voltage thereof
12/08/2005US20050270858 Plural circuit selection using role reversing control inputs
12/08/2005US20050270856 Multi-level format for information storage
12/08/2005US20050270855 Data protection system
12/08/2005US20050270854 Methods of modifying operational characteristic of memory devices using control bits received through data pins and related devices and systems
12/08/2005US20050270853 Memory module and method for accessing the same
12/08/2005US20050270831 Magnetic non-volatile memory coil layout architecture and process integration scheme
12/08/2005US20050270823 Standard cell, semiconductor integrated circuit device of standard cell scheme and layout design method for semiconductor integrated circuit device
12/08/2005US20050270819 Semiconductor storage device
12/08/2005US20050270758 Semiconductor device, noise reduction method, and shield cover
12/08/2005US20050270074 Power-gating system and method for integrated circuit devices
12/08/2005US20050270058 System for testing integrated circuit devices
12/08/2005US20050268774 Frequency spectrum conversion to natural harmonic frequencies process
12/07/2005CN1230825C EEPROM memory chip with multiple use pinouts
12/06/2005US6972988 State save-on-power-down using GMR non-volatile elements
12/06/2005US6972981 Semiconductor memory module
12/06/2005US6972980 Semiconductor memory devices and methods of fabricating semiconductor memory device
12/06/2005US6972979 Nonvolatile memory
12/06/2005US6972526 Organic EL display device and driving circuits
12/06/2005US6972465 CMOS process compatible, tunable negative differential resistance (NDR) device and method of operating same
12/01/2005WO2005114667A2 Internal voltage generator scheme and power management method
12/01/2005US20050265111 High voltage generation and regulation circuit in a memory device
12/01/2005US20050265086 Semiconductor storage device
12/01/2005US20050265083 Method and system for monitoring a supply-chain
12/01/2005US20050265082 Simultaneous read circuit for multiple memory cells
12/01/2005US20050265062 Chip to chip interface
12/01/2005US20050263811 Semiconductor device
12/01/2005DE102004022425A1 Integrierte Schaltungsanordnung zur Stabilisierung einer Spannung An integrated circuit device for stabilizing a voltage
11/2005
11/29/2005US6971032 Supplying multiple voltages via three power supply terminals to a semiconductor device that is connectable to a host device and a peripheral device
11/29/2005US6970391 Semiconductor device incorporating internal power supply for compensating for deviation in operating condition and fabrication process conditions
11/29/2005US6970371 Reference generator system and methods for reading ferroelectric memory cells using reduced bitline voltages
11/29/2005US6970369 Memory device
11/29/2005US6970035 Charge pump circuit
11/29/2005US6970019 Semiconductor integrated circuit device having power reduction mechanism
11/29/2005US6969894 Variable threshold semiconductor device and method of operating same
11/29/2005US6969883 Non-volatile memory having a reference transistor
11/24/2005WO2005112035A2 Nonvolatile memory array organization and usage
11/24/2005WO2005091907A3 Communication network for providing emergency services
11/24/2005WO2005033839A3 Device control system, method, and apparatus
11/24/2005US20050262388 Memory controllers with interleaved mirrored memory modes
11/24/2005US20050262369 Semiconductor memory device, and method of controlling the same
11/24/2005US20050262286 Intelligent memory device multilevel ASCII interpreter
11/24/2005US20050261601 Method and system for processing neuro-electrical waveform signals
11/24/2005US20050259504 DRAM interface circuits having enhanced skew, slew rate and impedance control
11/24/2005US20050259501 Synchronous global controller for enhanced pipelining
11/24/2005US20050259500 Semiconductor memory device and semiconductor device
11/24/2005US20050259499 Semiconductor memory device having a global data bus
11/24/2005US20050259497 Internal voltage generator scheme and power management method
11/24/2005US20050259496 Throttling memory in a computer system
11/24/2005US20050259495 Multiple-time programmable resistance circuit
11/24/2005US20050259489 Semiconductor memory device
11/24/2005US20050259483 Genes and polypeptides relating to prostate cancers
11/24/2005US20050259482 Actuator driving apparatus
11/24/2005US20050259480 Method and apparatus for providing debug functionality in a buffered memory channel
11/24/2005US20050259478 Memory device including self-ID information
11/24/2005US20050259476 L0 cache alignment circuit
11/24/2005US20050259466 Semiconductor memory device with signal lines arranged across memory cell array thereof
11/24/2005US20050259459 Wafer dividing method
11/24/2005US20050259458 Method and system of encrypting/decrypting data stored in one or more storage devices
11/24/2005US20050259457 Semiconductor device and method for manufacturing the same
11/24/2005US20050258880 Internal reset signal generator for use in semiconductor memory
11/24/2005DE69034191T2 EEPROM-System mit aus mehreren Chips bestehender Blocklöschung EEPROM system with an existing block of several chips deletion
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