Patents
Sitemap › G11 - Information storage › G11C - Static stores › G11C 5 - Details of stores covered by group
Patents for G11C 5 - Details of stores covered by group (20,391)
01/2006
01/10/2006US6985376 Nonvolatile semiconductor storage apparatus having reduced variance in resistance values of each of the storage states
01/10/2006US6985363 Card type recording medium and production method therefor
01/10/2006US6985027 Voltage step down circuit with reduced leakage current
01/10/2006US6985023 Selective switching of a transistor's back gate potential
01/10/2006US6984561 Method for making high density nonvolatile memory
01/05/2006US20060003715 Circuit and method for adjusting threshold drift over temperature in a CMOS receiver
01/05/2006US20060002166 Semiconductor memory device, electronic card and electronic device
01/05/2006US20060002165 High speed memory modules utilizing on-trace capacitors
01/05/2006US20060001629 Display controller, electronic equipment and method for supplying image data
01/05/2006US20060001131 Memory device power distribution in memory assemblies
01/05/2006DE102005015828A1 Hub for memory module e.g. fully buffered dual-in-line memory module, has controller which ignores memory identification information in response to southbound packet from memory controller when writing packet data during test mode
01/05/2006DE102004028076A1 Integrated semiconductor memory, has voltage generators for providing identical electric potential, where generators are arranged in direct proximity to respective memory cell array
01/04/2006EP1612667A2 Method and apparatus for loading an in-place executable file into a virtual machine
01/04/2006CN1716602A Stacked semiconductor memory device
01/04/2006CN1716599A Three-dimensional semiconductor device provided with interchip interconnection selection means
01/04/2006CN1716454A Flash memory device including bit line voltage clamp circuit for controlling bit line voltage during programming, and bit line voltage control method thereof
01/04/2006CN1716447A Semiconductor memory device for low power consumption
01/04/2006CN1716147A Hierarchical module
01/04/2006CN1235226C High capacity memory module with built-in high speed bus terminations
01/03/2006US6983388 Method and apparatus for reducing leakage power in a cache memory by using a timer control signal that removes power to associated cache lines
01/03/2006US6982921 Multiple configuration multiple chip memory device and method
01/03/2006US6982893 Memory module having a plurality of integrated memory components
12/2005
12/29/2005WO2005122882A2 Method and system for processing neuro-electrical waveform signals
12/29/2005WO2005094405A3 Closed loop dynamic power management
12/29/2005US20050289292 System and method for thermal throttling of memory modules
12/29/2005US20050289286 Multi-core processor control method
12/29/2005US20050289285 Method and apparatus for loading relocatable in-place executable files in a virtual machine
12/29/2005US20050289283 Autonomic computing utilizing a sequestered processing resource on a host CPU
12/29/2005US20050287736 Latch-up prevention for memory cells
12/29/2005US20050286692 Domestic origination to international termination country set logic
12/29/2005US20050286336 Flash EEprom system
12/29/2005US20050286334 Stacked semiconductor memory device
12/29/2005US20050286333 High-voltage tolerant input buffer circuit
12/29/2005US20050286322 Cascade wake-up circuit preventing power noise in memory device
12/29/2005US20050286310 Charge pump circuitry having adjustable current outputs
12/29/2005US20050286302 Flash memory device including bit line voltage clamp circuit for controlling bit line voltage during programming, and bit line voltage control method thereof
12/29/2005US20050286295 Memory cell array latchup prevention
12/29/2005US20050286288 Latch-up prevention for memory cells
12/29/2005US20050286286 Three-dimensional semiconductor device provided with interchip interconnection selection means for electrically isolating interconnections other than selected interchip interconnections
12/29/2005US20050286285 Semiconductor memory device and method of arranging signal and power lines thereof
12/29/2005US20050286284 Method and system for expanding flash storage device capacity
12/29/2005US20050286283 Method and system for expanding flash storage device capacity
12/29/2005US20050285665 Integrated floating power transfer device with logic level control and method
12/29/2005US20050285664 Integrated floating power transfer device with electromagnetic emission control circuit and method
12/29/2005US20050285248 Method and system for expanding flash storage device capacity
12/29/2005US20050285174 Stacked semiconductor memory device
12/29/2005DE102005022687A1 Semiconductor memory system has dynamic RAM (DRAM) that generates mirror mode control signal in response to chip reset signal and one of non-shared command signal received from memory controller, to operate DRAM in normal or mirror modes
12/29/2005DE102004046549A1 High voltage generating circuit for use in semiconductor memory device, has ripple reduction circuit limiting voltage level of high voltage applied from pumping output terminal of pump when pump is in one operating mode
12/29/2005DE102004027273A1 Halbleiterbaustein mit einer ersten und mindestens einer weiteren Halbleiterschaltung und Verfahren A semiconductor device having a first and at least a further semiconductor circuit and method
12/29/2005DE102004026808A1 Abwärtskompatibler Speicherbaustein Compatible memory module downward
12/29/2005CA2569877A1 Method and system for processing neuro-electrical waveform signals
12/28/2005EP1610344A1 Product and method preventing incorrect storage of data in case of power-down
12/27/2005US6980474 Semiconductor memory device
12/27/2005US6980472 Device and method to read a 2-transistor flash memory cell
12/27/2005US6980465 Addressing circuit for a cross-point memory array including cross-point resistive elements
12/27/2005US6980462 Memory cell architecture for reduced routing congestion
12/27/2005US6980456 Memory with low and fixed pre-charge loading
12/27/2005US6980448 DRAM boosted voltage supply
12/27/2005US6980048 Voltage generating circuit capable of supplying stable output voltage regardless of external input voltage
12/27/2005US6979983 Voltage regulator
12/22/2005US20050283688 Method and apparatus for testing a memory array
12/22/2005US20050281117 Nonvolatile semiconductor memory device
12/22/2005US20050281115 On-chip EE-PROM programming waveform generation
12/22/2005US20050281114 Shared decoupling capacitance
12/22/2005US20050281106 Semiconductor memory device for low power consumption
12/22/2005US20050281098 Staggered memory cell array
12/22/2005US20050281096 High-density memory module utilizing low-density memory components
12/22/2005US20050281094 Semicondutor memory device and array internal power voltage generating method thereof
12/22/2005US20050281093 Charge pump for programmable semiconductor memory
12/22/2005US20050281074 Input return path based on VDDQ/VSSQ
12/22/2005US20050281071 Word line driver circuits for use in semiconductor memory and driving method thereof
12/22/2005US20050280461 Level shifter circuit with stress test function
12/22/2005US20050280450 Power-up reset circuit
12/22/2005US20050280131 Memory card
12/22/2005US20050280049 Metal-poly integrated capacitor structure
12/22/2005US20050280036 Semiconductor product having a first and at least one further semiconductor circuit and method
12/22/2005DE102005023881A1 Allgemeines serielles Schnittstellensystem General serial interface system
12/22/2005DE102005018110A1 Chip-zu-Chip-Schnittstelle Chip-to-chip interface
12/22/2005DE102004025899A1 Electronic control arrangement, has control module with control units e.g. dynamic random access memories, having decoder units to decode bit string of signal, and connecting wire to connect each control unit with signal producing unit
12/22/2005DE102004025556A1 Electronic memory device, has interface unit that connects memory cell fields with respective external circuit units, and switching unit for switching external data line to memory field or system information memory unit
12/21/2005EP1201033B1 Circuit configuration for supplying power to an integrated circuit via a pad
12/21/2005CN1711689A Integrated floating power transfer device with electromagnetic emission control circuit and method
12/21/2005CN1711688A Integrated floating power transfer device with logic level control and method
12/21/2005CN1710665A Shared decoupling capacitance
12/21/2005CN1232986C Internal voltage level control circuit and semiconductor memory device and their control method
12/20/2005US6978345 Self-mirroring high performance disk drive
12/20/2005US6977865 Method and circuit for controlling operation mode of PSRAM
12/20/2005US6977860 SRAM power reduction
12/20/2005US6977850 Semiconductor device having switch circuit to supply voltage
12/20/2005US6977838 Method and system for providing a programmable current source for a magnetic memory
12/20/2005US6977834 Semiconductor integrated circuit device
12/20/2005US6977833 CMOS isolation cell for embedded memory in power failure environments
12/20/2005US6977832 Semiconductor memory device capable of improving quality of voltage waveform given in a signal interconnection layer
12/15/2005WO2005119686A2 Method of increasing ddr memory bandwidth in ddr sdram modules
12/15/2005WO2005024560A3 Multiple processor system and method including multiple memory hub modules
12/15/2005US20050278592 Semiconductor memory
12/15/2005US20050278474 Method of increasing DDR memory bandwidth in DDR SDRAM modules
12/15/2005US20050278473 Method and apparatus for processing data in a processing unit being a thread in a multithreading environment
12/15/2005US20050277243 Flash memory having a high-permittivity tunnel dielectric
12/15/2005US20050277241 Semiconductor device and ic card
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