Patents
Sitemap › G11 - Information storage › G11C - Static stores › G11C 16 - Erasable programmable read-only memories
Patents for G11C 16 - Erasable programmable read-only memories (44,373)
06/2005
06/15/2005CN1628355A Reading circuit for reading a memory cell
06/15/2005CN1628289A Memory mapping device utilizing sector pointers
06/15/2005CN1628032A Ink jet printhead chip with predetermined micro-electromechanical systems height
06/15/2005CN1627942A Process for isolating srtemisinin from artemisia annua
06/15/2005CN1627516A Test module and test method in use for electrical erasable memory built in chip
06/15/2005CN1627448A Charge pump in use for circuit of non-volatility memory
06/15/2005CN1627447A Non-volatile semiconductor memory device adapted to store a multi-valued in a single memory cell
06/15/2005CN1627446A Method for programming P channel electrically erasable programmable read only memory
06/15/2005CN1206658C Semiconductor device
06/15/2005CN1206657C Flash memory
06/15/2005CN1206655C Read amplifier
06/14/2005US6907544 Method for operating memory devices for storing data
06/14/2005US6907497 Non-volatile semiconductor memory device
06/14/2005US6906974 Sense amplifiers with output buffers and memory devices incorporating same
06/14/2005US6906966 Fast discharge for program and verification
06/14/2005US6906961 Erase block data splitting
06/14/2005US6906960 Semiconductor memory device
06/14/2005US6906959 Method and system for erasing a nitride memory device
06/14/2005US6906958 Word-line voltage generator
06/14/2005US6906957 Sensing circuitry for reading and verifying the contents of electrically programmable and erasable non-volatile memory cells, useful in low supply-voltage technologies
06/14/2005US6906955 Flash memory with RDRAM interface
06/14/2005US6906954 Semiconductor integrated circuit and nonvolatile memory element
06/14/2005US6906953 Vertical NROM having a storage density of 1 bit per 1F2
06/14/2005US6906939 Re-writable memory with multiple memory layers
06/14/2005US6906376 EEPROM cell structure and array architecture
06/14/2005US6905926 Method of making nonvolatile transistor pairs with shared control gate
06/12/2005CA2489637A1 Electronic data processing device
06/09/2005WO2005053020A1 Apparatus and method for vertical split-gate nrom memory
06/09/2005WO2005052947A1 Compressed event counting technique and application to a flash memory system
06/09/2005WO2005052946A1 Embedded memory with security row lock protection
06/09/2005WO2005052799A2 System and method for operating dual bank read-while-write flash
06/09/2005WO2005027134A3 Multiple bit chalcogenide storage device
06/09/2005WO2005001899A3 Non-volatile electromechanical field effect devices and circuits using same and methods of forming same
06/09/2005WO2004107399A3 Transistor with independant gate structures
06/09/2005US20050125708 Method for streamlining error connection code computation while reading or programming a NAND flash memory
06/09/2005US20050125595 Non-volatile semiconductor memory
06/09/2005US20050124115 Method of forming a floating gate for a stacked gate flash memory device
06/09/2005US20050122816 Storage device using resistance varying storage element and reference resistance value decision method for the device
06/09/2005US20050122808 Low voltage sense amplifier for operation under a reduced bit line bias voltage
06/09/2005US20050122791 Storage subsystem with embedded circuit for protecting against anomalies in power signal from host
06/09/2005US20050122790 Memory controller
06/09/2005US20050122783 Methods of erasing a non-volatile memory device having discrete charge trap sites
06/09/2005US20050122780 NAND memory array incorporating multiple write pulse programming of individual memory cells and method for operation of same
06/09/2005US20050122779 Memory array incorporating memory cells arranged in NAND strings
06/09/2005US20050122778 Electronic memory circuit and related manufacturing method
06/09/2005US20050122776 Novel monolithic, combo nonvolatile memory allowing byte, page and block write with no disturb and divided-well in the cell array using a unified cell structure and technology with a new scheme of decoder and layout
06/09/2005US20050122771 Memory device and method of operating same
06/09/2005US20050122759 Memory cell with non-destructive one-time programming
06/09/2005US20050122757 Memory architecture and method of manufacture and operation thereof
06/09/2005US20050122756 Semiconductor memory device
06/09/2005US20050121716 Flash memory device
06/09/2005US20050121712 Flash memory cell and method of manufacturing the same and programming/erasing/reading method of flash memory cell
06/09/2005US20050121697 Storage device
06/09/2005US20050121659 Non-volatile memory and the fabrication method thereof
06/09/2005DE19654561B4 Speicherzellenfeld Memory cell array
06/09/2005DE102004052200A1 Mehrstufige Ladungspumpenschaltung Multi-stage charge pump circuit
06/08/2005EP1538633A2 Flash memory device and method for programming the same
06/08/2005EP1538632A1 Phase change memory device with overvoltage protection and method for protecting a phase change memory device against overvoltages
06/08/2005EP1538525A1 ECC computation simultaneously performed while reading or programming a flash memory
06/08/2005EP1537671A2 Dac-based voltage regulator for flash memory array
06/08/2005EP1537585A1 Memory cell
06/08/2005EP1537584A1 Programming a phase-change material memory
06/08/2005EP1468424B1 Method and apparatus for soft program verification in a memory device
06/08/2005CN1625781A Non-volatile storage device
06/08/2005CN1624904A Non-volatile momery body and its operation method
06/08/2005CN1624803A 半导体集成电路装置 The semiconductor integrated circuit device
06/08/2005CN1205617C Buff circuit
06/07/2005US6904552 Circuit and method for test and repair
06/07/2005US6904400 Flash EEPROM memory emulator of non-flash EEPROM device and corresponding method
06/07/2005US6904325 Method for optimizing ECU parallel flash programming arrangement on a CAN-based vehicle serial bus in general assembly
06/07/2005US6903983 Semiconductor integrated circuit device and read start trigger signal generating method therefor
06/07/2005US6903981 Non-volatile semiconductor memory device, method for sub-block erase and electric device with the same
06/07/2005US6903980 Nonvolatile semiconductor memory device capable of correcting over-erased memory cells
06/07/2005US6903979 Efficient method of PMOS stacked-gate memory cell programming utilizing feedback control of substrate current
06/07/2005US6903978 Method of PMOS stacked-gate memory cell programming enhancement utilizing stair-like pulses of control gate voltage
06/07/2005US6903977 Nonvolatile semiconductor memory device and method of producing the same
06/07/2005US6903975 Nonvolatile semiconductor memory device
06/07/2005US6903974 Flash memory device with a variable erase pulse
06/07/2005US6903972 Different methods applied for archiving data according to their desired lifetime
06/07/2005US6903971 Non-volatile semiconductor memory device
06/07/2005US6903970 Flash memory device with distributed coupling between array ground and substrate
06/07/2005US6903969 One-device non-volatile random access memory cell
06/07/2005US6903967 Memory with charge storage locations and adjacent gate structures
06/07/2005US6903595 High voltage transfer circuit
06/07/2005US6903405 Semiconductor memory device with a pair of floating gates
06/07/2005US6903361 Non-volatile memory structure
06/02/2005WO2005050734A1 Charge-trapping memory device, operating and manufacturing
06/02/2005WO2005050665A1 Semiconductor integrated circuit
06/02/2005WO2005041206A3 Method, system and circuit for programming a non-volatile memory array
06/02/2005WO2005017907A3 Read bias scheme for phase change memories
06/02/2005WO2004090905A3 Three-dimensional memory device incorporating segmented bit line memory array
06/02/2005US20050120266 Memory device with sector pointer structure
06/02/2005US20050120186 Memory system and process for controlling a memory component to achieve different kinds of memory characteristics on one and the same memory component
06/02/2005US20050120159 Integrated memory device with multiple reading and writing commands
06/02/2005US20050119123 reversible phase change between electrically or optically detectable states can be caused by electric energy or electromagnetic energy; recording material has a crystal structure including lattice defects
06/02/2005US20050117446 Semiconductor memory device and semiconductor memory device control method
06/02/2005US20050117444 Multiple use memory chip
06/02/2005US20050117419 Method of evaluating characteristics of semiconductor memory element, and method of extracting model parameter of semiconductor memory element
06/02/2005US20050117406 Semiconductor integrated circuit device with main cell array and fuse cell array
06/02/2005US20050117401 Techniques of recovering data from memory cells affected by field coupling with adjacent memory cells
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