| Patents for G06F 7 - Methods or arrangements for processing data by operating upon the order or content of the data handled (93,043) |
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| 05/18/1988 | EP0267836A1 Algebraic coder of Reed-Solomon and BCH block codes for use in digital telecommunication |
| 05/18/1988 | EP0267729A2 An orthogonal transform processor |
| 05/18/1988 | EP0267448A2 Full adder circuit |
| 05/18/1988 | EP0267425A2 Digital binary array multipliers |
| 05/18/1988 | EP0267271A1 In-system programmable logic device. |
| 05/18/1988 | EP0157075B1 Modular data processing system |
| 05/17/1988 | US4745570 Binary multibit multiplier |
| 05/17/1988 | US4745569 Decimal multiplier device and method therefor |
| 05/17/1988 | US4745568 Computational method and apparatus for finite field multiplication |
| 05/17/1988 | US4745306 Half adder having a pair of precharged stages |
| 05/11/1988 | DE3638257A1 Adder circuit using decimal 1-out-of-10 code |
| 05/11/1988 | DE3628830A1 Adder circuit using decimal 1-out-of-10 code |
| 05/10/1988 | US4744045 Divider circuit for encoded PCM samples |
| 05/10/1988 | US4744043 Data processor execution unit which receives data with reduced instruction overhead |
| 05/10/1988 | EP0168406A4 Floating point condition code generation. |
| 05/05/1988 | WO1988003292A1 Data alignment system |
| 05/04/1988 | EP0266267A1 Sequential memory addressing method |
| 05/04/1988 | EP0265555A1 Method and circuitry for addition of floating point numbers |
| 05/03/1988 | USH472 Method and apparatus for processing binary-coded/packed decimal data |
| 05/03/1988 | US4742520 ALU operation: modulo two sum |
| 05/03/1988 | US4742480 Cycle counter/shifter for division |
| 05/03/1988 | US4742479 Modulo arithmetic unit having arbitrary offset and modulo values |
| 05/03/1988 | US4742453 Pipeline-controlled information processing system for generating updated condition code |
| 05/03/1988 | CA1236220A1 Multiplier circuitry using pass transistors |
| 04/28/1988 | DE3635749A1 Adder circuit using decimal 1-out-of-10 code |
| 04/27/1988 | EP0265336A1 Galois field polynomial processing device and digital signal processor comprising such a device |
| 04/27/1988 | EP0265180A2 Multiplier in a galois field |
| 04/26/1988 | US4740993 Digital companding circuit |
| 04/26/1988 | US4740907 Full adder circuit using differential transistor pairs |
| 04/26/1988 | US4740906 Digital lattice filter with multiplexed fast adder/full adder for performing sequential multiplication and addition operations |
| 04/26/1988 | US4740891 Asynchronous state machine |
| 04/26/1988 | US4740789 Method for optimizing the storage of video signals in a digital scan converter, and a digital scan converter using said method |
| 04/26/1988 | US4740721 Programmable logic array with single clock dynamic logic |
| 04/21/1988 | DE3635074A1 Memory arrangement with memory array |
| 04/21/1988 | DE3634983A1 Addition constant value circuit in decimal 1-out-of-10 code |
| 04/21/1988 | DE3626369A1 Adder circuit in decimal 1-out-of-10 code |
| 04/20/1988 | EP0264256A2 Apparatus and method for approximating the magnitude of a complex number |
| 04/20/1988 | EP0264130A2 Barrel shifter |
| 04/20/1988 | EP0264077A2 Buffer address register |
| 04/20/1988 | EP0264048A2 Thirty-two bit bit-slice |
| 04/19/1988 | US4739503 Digital arithmetic combiner |
| 04/14/1988 | DE3627749A1 Adder circuit for decimal 1 out of 10 code - has main circuit of adder stages operating with correction stage dependent upon values |
| 04/14/1988 | DE3617649A1 Adder circuit in decimal 1-out-of-10 code |
| 04/12/1988 | US4737933 CMOS multiport general purpose register |
| 04/12/1988 | US4737926 Optimally partitioned regenerative carry lookahead adder |
| 04/07/1988 | DE3632232A1 Arrangement for multiplying a frequency by a fraction |
| 04/06/1988 | EP0262944A2 Error correction apparatus |
| 04/06/1988 | EP0262674A2 Microcomputer having Z-flag capable of detecting coincidence at high speed |
| 04/06/1988 | EP0262636A2 Circuit arrangement for selecting and/or aligning data units in data processors |
| 04/05/1988 | US4736335 Multiplier-accumulator circuit using latched sums and carries |
| 04/05/1988 | US4736334 Circuit for calculating the value of a complex digital variable |
| 04/05/1988 | US4736333 Electronic musical instrument |
| 04/05/1988 | US4736288 Data processing device |
| 03/31/1988 | DE3632182A1 Adder circuit using decimal 1-out-of-10 code |
| 03/31/1988 | DE3632181A1 Adder circuit in decimal 1-out-of-10 code |
| 03/30/1988 | EP0262032A1 Binary adder having a fixed operand, and a parallel/serial multiplier comprising such an adder |
| 03/30/1988 | EP0261954A2 Digital signal gain control circuitry |
| 03/30/1988 | EP0261390A2 Matrix concatenation in a graphics display system |
| 03/29/1988 | US4734921 Fully programmable linear feedback shift register |
| 03/29/1988 | US4734878 Circuit for performing square root functions |
| 03/29/1988 | US4734877 Vector processing system |
| 03/29/1988 | US4734876 Circuit for selecting one of a plurality of exponential values to a predetermined base to provide a maximum value |
| 03/24/1988 | WO1988002145A1 Digital processing of sensor signals for reading binary storage media |
| 03/24/1988 | WO1988002144A1 Arrangement for data compression |
| 03/24/1988 | WO1988001079A3 Signal processing |
| 03/24/1988 | DE3632074A1 Adder circuit using decimal 1-out-of-10 code |
| 03/24/1988 | DE3631380A1 Adder circuit using decimal 1-out-of-10 code |
| 03/23/1988 | EP0260618A2 Method and device for obtaining sum of products using integrated circuit |
| 03/23/1988 | EP0260540A2 Random number generator circuit arrangement for scrambled-data transmission |
| 03/23/1988 | EP0260515A2 Digital multiplier architecture with triple array summation of partial products |
| 03/23/1988 | EP0260413A2 Circuit combining functions of cyclic redundancy check code and pseudo-random number generators |
| 03/23/1988 | EP0260409A2 Data processing system with two execution units |
| 03/23/1988 | EP0260289A1 Process and device for selectively duplicating alphanumeric and/or graphic characters. |
| 03/23/1988 | EP0260281A1 Optical data processing systems and methods for matrix inversion, multiplication, and addition. |
| 03/22/1988 | US4733395 Digital word generator |
| 03/22/1988 | US4733365 Logic arithmetic circuit |
| 03/22/1988 | US4733349 Method for recording and managing processing history information using a plurality of storage devices |
| 03/17/1988 | DE3630605A1 CMOS semiconductor arrangement as EXOR-NOR circuit, particularly as chip for a CMOS-type full adder stage |
| 03/17/1988 | DE3620232A1 Serial addition-subtraction unit in decimal 1-out-of-10 code |
| 03/16/1988 | EP0259514A1 Digital circuit for the simultaneous generation of digital sine and cosine function values |
| 03/15/1988 | US4731737 High speed intelligent distributed control memory system |
| 03/09/1988 | EP0258653A2 Dynamic programmable logic arrays with NOR-NOR structure implemented in C-MOS technology |
| 03/08/1988 | US4730319 Device for transforming the occurrence probability of logic vectors and for the generation of vector sequences with time variable probabilities |
| 03/08/1988 | US4730266 Logic full adder circuit |
| 03/08/1988 | CA1233905A1 Decimal digit processing apparatus and method |
| 03/08/1988 | CA1233901A1 Arrangement for two-dimensional dpcm-coding |
| 03/03/1988 | DE3629739A1 Adder circuit using decimal 1-out-of-10 code |
| 03/03/1988 | DE3628831A1 Adder circuit using decimal 1-out-of-10 code |
| 03/02/1988 | EP0258051A2 Digital signal processor with divide function |
| 03/02/1988 | EP0257650A2 Microprocessor |
| 03/02/1988 | EP0257362A1 Adder |
| 03/02/1988 | CN86105812A Wide band multiplier |
| 03/01/1988 | US4728927 Apparatus and method for performing comparison of two signals |
| 03/01/1988 | US4728827 Static PLA or ROM circuit with self-generated precharge |
| 02/25/1988 | DE3628049A1 Adder circuit using decimal 1-out-of-10 code - has main adder, auxiliary circuit with dual half adder, and number alteration stage |
| 02/24/1988 | EP0256455A1 Fast division method for long operands in data processing equipments, and circuit therefor |
| 02/24/1988 | EP0256358A2 Accelerated validity response permitting early issue of instructions dependent upon outcome of floating point operations |
| 02/23/1988 | US4727570 Waveform generators |
| 02/23/1988 | US4727507 Multiplication circuit using a multiplier and a carry propagating adder |
| 02/23/1988 | US4727506 Digital scaling circuitry with truncation offset compensation |