| Patents for G06F 7 - Methods or arrangements for processing data by operating upon the order or content of the data handled (93,043) |
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| 08/03/1988 | EP0276520A1 Method of testing a modified booth multiplier, modified booth multiplier suitable for testing by means of this method, and integrated circuit comprising such a modified booth multiplier |
| 08/02/1988 | US4761760 Digital adder-subtracter with tentative result correction circuit |
| 08/02/1988 | US4761759 Absolute value comparator for differences |
| 08/02/1988 | US4761758 Digital signal processor with divide function |
| 08/02/1988 | US4761757 Carry-save-adder three binary dividing apparatus |
| 08/02/1988 | US4761756 Signed multiplier with three port adder and automatic adjustment for signed operands |
| 08/02/1988 | US4761755 Data processing system and method having an improved arithmetic unit |
| 08/02/1988 | US4761751 Method and apparatus for generating digital signals representing periodic samples of a sine wave |
| 08/02/1988 | US4761729 Device for exchanging data between a computer and a peripheral unit having a memory formed by shift registers |
| 08/02/1988 | US4761641 Information display system |
| 08/02/1988 | CA1240063A1 Digital companding circuit |
| 07/27/1988 | EP0275979A2 Circuit for computing the quantized coefficient discrete cosine transform of digital signal samples |
| 07/26/1988 | US4760551 Operation unit for floating point data with variable exponent-part length |
| 07/26/1988 | US4760550 For dividing a pair of binary coded hexidecimal floating point numbers |
| 07/26/1988 | US4760544 Arithmetic logic and shift device |
| 07/26/1988 | US4760543 Orthogonal transform processor |
| 07/26/1988 | US4760526 Method for storing data into a file device and for data retrieval |
| 07/26/1988 | US4760517 Thirty-two bit, bit slice processor |
| 07/26/1988 | US4760374 Bounds checker |
| 07/19/1988 | US4758981 Signal sorting element with internal signal address value sorting criterion |
| 07/19/1988 | US4758975 Data processor capable of processing floating point data with exponent part of fixed or variable length |
| 07/19/1988 | US4758974 Most significant digit location |
| 07/19/1988 | US4758973 Apparatus for processing floating-point data having exponents of a variable length |
| 07/19/1988 | US4758972 Precision rounding in a floating point arithmetic unit |
| 07/19/1988 | US4758747 Programmable logic device with buried registers selectively multiplexed with output registers to ports, and preload circuitry therefor |
| 07/19/1988 | US4758746 Programmable logic array with added array of gates and added output routing flexibility |
| 07/14/1988 | WO1988005189A1 N-bit sum-carry accumulator |
| 07/14/1988 | DE3700065A1 Dual full adder |
| 07/14/1988 | DE3700063A1 Negating-complementing circuit in 51111 code |
| 07/14/1988 | DE3644800A1 Negating-complementing circuit using 5211 code |
| 07/13/1988 | EP0274392A2 Improved relational data base system |
| 07/13/1988 | EP0274323A1 Integrated signal-processing circuit for line and column summation of matrices of numerical values |
| 07/13/1988 | EP0273968A1 Programmably controlled partially distributed masking mechanism in a programmable unit having variable data path widths. |
| 07/13/1988 | EP0273921A1 Accumulating recursive computation |
| 07/12/1988 | US4757468 Authenticated read-only memory |
| 07/12/1988 | US4757467 Apparatus for estimating the square root of digital samples |
| 07/12/1988 | US4757464 Apparatus for recognizing relative extrema |
| 07/07/1988 | DE3644573A1 Negating-complementing circuit using 5211 code |
| 07/07/1988 | DE3644570A1 Adder circuit using 54321 code |
| 07/07/1988 | DE3644568A1 Adder circuit using 51111 code |
| 07/06/1988 | EP0273802A2 Digital rank-order filter and associated filtering method |
| 07/06/1988 | EP0273753A2 Floating-point arithmetic apparatus |
| 07/06/1988 | EP0273637A2 Bit pattern conversion system |
| 07/05/1988 | US4755969 Pseudo random sequence generation |
| 07/05/1988 | US4755965 Processor to carry out data processing in different modes and multiplication device suitable for such a processor |
| 07/05/1988 | US4755962 Microprocessor having multiplication circuitry implementing a modified Booth algorithm |
| 07/05/1988 | US4754862 Coin discrimination apparatus |
| 07/05/1988 | CA1238983A1 Method for refreshing multicolumn tables in a relational data base using minimal information |
| 06/30/1988 | WO1988004805A1 Computational method and apparatus for finite field multiplication |
| 06/30/1988 | DE3643346A1 Adder circuit using 5211 code |
| 06/28/1988 | US4754424 Information processing unit having data generating means for generating immediate data |
| 06/28/1988 | US4754422 Dividing apparatus |
| 06/28/1988 | US4754421 Multiple precision multiplication device |
| 06/28/1988 | US4754420 Digital data filter for local area network |
| 06/28/1988 | US4754412 Arithmetic logic system using the output of a first alu to control the operation of a second alu |
| 06/23/1988 | DE3643379A1 Raising and code conversion circuit |
| 06/23/1988 | DE3642011A1 Adder circuit using decimal 1-out-of-10 code |
| 06/23/1988 | DE3642010A1 Adder circuit using 51111 code |
| 06/21/1988 | US4752905 High-speed multiplier having carry-save adder circuit |
| 06/21/1988 | US4752901 Arithmetic logic unit utilizing strobed gates |
| 06/21/1988 | US4752763 Binary comparison circuit with selectable binary digit override |
| 06/16/1988 | DE3642815A1 Adder circuit using decimal 1-out-of-10 code |
| 06/16/1988 | DE3642054A1 Dual full adder |
| 06/16/1988 | DE3642053A1 Adder circuit using 54321 code |
| 06/15/1988 | EP0271255A2 High-speed binary and decimal arithmetic logic unit |
| 06/15/1988 | EP0271082A2 Galois field arithmetic logic unit |
| 06/15/1988 | EP0270617A1 Programmable logic array |
| 06/14/1988 | US4751675 Memory access circuit with pointer shifting network |
| 06/14/1988 | US4751671 Size configurable data storage system |
| 06/14/1988 | US4751665 For calculating sums of floating point summands |
| 06/14/1988 | US4751631 Apparatus for fast generation of signal sequences |
| 06/09/1988 | DE3640809A1 Adder circuit using decimal 1-out-of-10 code |
| 06/09/1988 | DE3640462A1 Adder circuit using decimal 1-out-of-10 code |
| 06/09/1988 | DE3640455A1 Partial circuit for adder circuits using decimal 1-out-of-10 code or other codes |
| 06/09/1988 | DE3636556A1 Adder circuit using decimal 1-out-of-10 code |
| 06/08/1988 | EP0270300A2 Static PLA or ROM circuit with self-generated precharge |
| 06/08/1988 | EP0270219A2 Reduced parallel EXCLUSIVE OR and EXCLUSIVE NOR gate |
| 06/08/1988 | EP0269974A2 Method and apparatus for detecting a predetermined bit pattern within a serial bit stream |
| 06/07/1988 | US4750146 Method and apparatus for compensating for the truncation error in a filtered signal by adding the error to the positive part of the signal and subtracting the error from the negative part of the signal |
| 06/07/1988 | US4750144 Real time pipelined system for forming the sum of products in the processing of video data |
| 06/07/1988 | US4750106 Disk volume data storage and recovery method |
| 06/07/1988 | US4749886 Reduced parallel EXCLUSIVE or and EXCLUSIVE NOR gate |
| 06/02/1988 | WO1988004097A1 Fully programmable linear feedback shift register |
| 05/31/1988 | US4748644 Timing apparatus for use in a data processing unit |
| 05/31/1988 | US4748640 Digital circuit with band limiting characteristics for modem |
| 05/31/1988 | US4748585 Method of operating an electronic computer processor |
| 05/31/1988 | US4748584 Parallel multiplier utilizing Booth's algorithm |
| 05/31/1988 | US4748583 Cell-structured digital multiplier of semi-systolic construction |
| 05/31/1988 | US4748582 Parallel multiplier array with foreshortened sign extension |
| 05/31/1988 | US4748581 Digital root extraction circuit |
| 05/31/1988 | US4748580 Multi-precision fixed/floating-point processor |
| 05/31/1988 | US4748576 Pseudo-random binary sequence generators |
| 05/31/1988 | US4748575 Circuit for detecting trailing zeros in numbers |
| 05/31/1988 | US4748438 Signal processing apparatus for selectively filtering digital signal parameter packets |
| 05/26/1988 | DE3639167A1 Adder circuit using decimal 1-out-of-10 code |
| 05/26/1988 | DE3635783A1 Addition constant value circuit using decimal 1-out-of-10 code |
| 05/25/1988 | EP0268435A2 Multinode reconfigurable pipeline computer |
| 05/25/1988 | EP0268123A2 Processor for the calculation of transcendental functions |
| 05/24/1988 | US4747067 Apparatus and method for approximating the magnitude of a complex number |
| 05/24/1988 | US4747066 Arithmetic unit |