Patents
Sitemap › G06 - Computing; Calculating; Counting › G06F - Electric digital data processing › G06F 12 - Accessing, addressing or allocating within memory systems or architectures
Patents for G06F 12 - Accessing, addressing or allocating within memory systems or architectures (152,539)
05/1991
05/22/1991EP0428264A2 A method for generating an access plan in a database system
05/22/1991EP0428149A2 Cache controller
05/22/1991EP0428079A2 Translation look aside buffer with parallel exception checking and update bypass
05/21/1991US5018110 Serial input/output semiconductor memory
05/21/1991US5018064 Virtual computer system
05/21/1991US5018063 Method for reducing cross-interrogate delays in a multiprocessor system
05/21/1991US5018061 Microprocessor with on-chip cache memory with lower power consumption
05/21/1991US5018060 Allocating data storage space of peripheral data storage devices using implied allocation based on user parameters
05/21/1991CA1284390C Apparatus and method for a page frame replacement in a data processing system having virtual memory addressing
05/21/1991CA1284389C Read in process memory apparatus
05/18/1991CA2030184A1 System and method for storing firmware in relocatable format
05/16/1991WO1991001024A3 A method and apparatus for information management in a computer system
05/15/1991EP0427601A1 Method for authenticating a microprocessor-card, and system for implementing it
05/15/1991EP0427558A2 Task switching system
05/15/1991EP0427425A2 Improved paged memory controller
05/15/1991EP0427023A2 Data transmission control apparatus for parallel processing system
05/15/1991EP0426983A2 Processor - I/O address expansion
05/15/1991EP0426764A1 Computer memory backup system
05/14/1991US5016226 Apparatus for generating a data stream
05/14/1991US5016169 Data processor capable of correctly re-executing instructions
05/14/1991US5016168 Method for storing into non-exclusive cache lines in multiprocessor systems
05/14/1991US5014982 Memory cartridge and game apparatus using the same
05/14/1991CA2029628A1 Translation look aside buffer with parallel exception checking and update bypass
05/14/1991CA1284228C Byte write error code method and apparatus
05/08/1991EP0426592A2 Cache memory access system with a memory bypass for write through read operations
05/08/1991EP0426386A2 Data destination facility
05/08/1991EP0426366A2 Method and apparatus for independently resetting processors and cache controllers in multiple processor systems
05/08/1991EP0426323A2 Portable, resource sharing file server using co-routines
05/08/1991EP0426271A2 Portable semiconductor storage device
05/08/1991EP0426270A2 Portable semiconductor memory device
05/08/1991EP0426161A2 Multiprocessor communication using reduced addressing lines
05/08/1991EP0425843A2 Enhanced locked bus cycle control in a cache memory computer system
05/08/1991EP0425771A2 An efficient mechanism for providing fine grain storage protection intervals
05/08/1991EP0425550A1 Memory control unit.
05/08/1991CN1012598B Hardware controlling method for"write enable" function of hard magnetic disk machine
05/07/1991US5014312 Security system for the protection of programming zones of a chip card
05/07/1991US5014311 Integrated circuit with an access-controlled data memory
05/07/1991US5014273 Bad data algorithm
05/07/1991US5014247 System for accessing the same memory location by two different devices
05/07/1991US5014240 Semiconductor memory device
05/07/1991US5014197 Assignment of files to storage device using macro and micro programming model which optimized performance of input/output subsystem
05/07/1991US5014195 Configurable set associative cache with decoded data element enable lines
05/07/1991US5014194 System for reducing I/O controller overhead by using a peripheral controller for producing read, write, and address translation request signals
05/07/1991US5014188 Cache memory controllor associated with microprocessor
05/07/1991US5014187 Adapting device for accommodating different memory and bus formats
05/04/1991CA2028551A1 Data destination facility
05/04/1991CA2028085A1 Paged memory controller
05/04/1991CA2027799A1 Method and apparatus for independently resetting processors and cache controllers in multiple processor systems
05/04/1991CA2026816A1 Enhanced locked bus cycle control in a cache memory computer system
05/04/1991CA2026771A1 Multiprocessor communication using reduced addressing lines
05/04/1991CA2025439A1 Internal cache microprocessor slowdown circuit with minimal system latency
05/02/1991EP0425421A2 Process and apparatus for manipulating a boundless data stream in an object oriented programming system
05/02/1991EP0425420A2 Process and apparatus for handling persistent objects in an object oriented programming system
05/02/1991EP0425415A2 Process and apparatus for preserving data integrity of a database
05/02/1991EP0425414A2 Method and apparatus for processing a complex hierarchy of data objects
05/02/1991EP0425413A2 Process and apparatus for processing time consuming queries in an object oriented database management system
05/02/1991EP0425412A2 Process and apparatus for handling time consuming and reusable queries in an object oriented database management system
05/02/1991EP0425222A2 Data base management system with data dictionary cache
05/02/1991EP0425188A2 Stack design for processor
05/02/1991EP0425181A2 Preference circuit for a computer system
05/02/1991EP0425168A2 An information searching system for image data
05/02/1991EP0425053A1 Data processing system having memory card authenticating means, electronic circuit for use in that system and method for using this authentication
05/02/1991EP0424911A2 Memory system having self-testing function
05/02/1991EP0424903A2 Data recording system
05/02/1991EP0424889A2 A memory management system for reallocating memory space based on data set in registers
05/02/1991EP0424432A1 Multiprocessor system including a hierarchical cache memory system
05/02/1991EP0424407A1 Intermediate spreadsheet structure.
05/02/1991DE4033981A1 Memory circuit board with semiconductor recording medium - has SRAM or EEPROM with preset wafer size for estimated storage capacity
05/02/1991DE4032571A1 Einrichtung zur behandlung von paritaetsfehlern in speichergruppen von personal computern Device for treatment of paritaetsfehlern in memory of personal computers groups
05/01/1991CN1051095A Personal computer memory bank parity error indicator
04/1991
04/30/1991US5012441 Apparatus for addressing memory with data word and data block reversal capability
04/30/1991US5012410 Data processor with instruction cache memory
04/30/1991US5012408 Memory array addressing system for computer systems with multiple memory arrays
04/30/1991US5012407 Computer system which accesses operating system information and command handlers from optical storage via an auxiliary processor and cache memory
04/30/1991US5012405 File management system for permitting user access to files in a distributed file system based on linkage relation information
04/25/1991DE4027202A1 Processor system with processor and memory control unit - has identification memories associated with memory modules, facilitates changing module capacities
04/24/1991EP0424191A2 Device and method for defect handling in semi-conductor memory
04/24/1991EP0424163A2 Translation look ahead based cache access
04/24/1991EP0424045A2 System and method for interacting with a database
04/24/1991EP0424031A2 Method and system for dynamically controlling the operation of a program
04/24/1991EP0423959A2 Recursive run array storage of data
04/24/1991EP0423933A2 Personal computer memory bank parity error indicator
04/24/1991EP0423725A2 Method and apparatus for concurrency control in database system
04/24/1991EP0423723A2 Data retrieval system for relational database
04/24/1991EP0423557A2 Cache management method and apparatus
04/24/1991EP0423453A2 Address translation and copying process
04/24/1991EP0169909B1 Auxiliary memory device
04/24/1991CN1050938A Access plan invalidation for database system
04/24/1991CN1050937A Enforcement of referential constraints in a database system
04/24/1991CN1050936A Preemption control for central processor with cache
04/24/1991CA2023617A1 Method and apparatus for processing a complex hierarchy of data objects
04/23/1991US5010483 Vector processor capable of indirect addressing
04/23/1991US5010481 Main memory control system for virtual machine
04/23/1991US5010476 Time multiplexed system for tightly coupling pipelined processors to separate shared instruction and data storage units
04/23/1991US5010475 Consistency ensuring system for the contents of a cache memory
04/23/1991CA1283487C Method and apparatus for determining in a computer which of a number of programmes are allowed to utilise a rapid access memory
04/18/1991WO1991005315A1 Page memory control in a raster image processor employed for digital halftoning
04/18/1991DE4031366A1 Electronic scales with processor and digital address circuit - has memory areas distributed according to boundary address
04/18/1991DE4030790A1 Abtastregister und testschaltkreis, der dieses benutzt Scan register and test circuitry that uses this
04/17/1991EP0422967A2 Dual domain memory controller
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