Patents
Sitemap › G06 - Computing; Calculating; Counting › G06F - Electric digital data processing › G06F 12 - Accessing, addressing or allocating within memory systems or architectures
Patents for G06F 12 - Accessing, addressing or allocating within memory systems or architectures (152,539)
09/1999
09/02/1999DE19807934A1 SIM-Karte mit Telefonbucheinträgen für Mobiltelefone SIM card phonebook entries for mobile phones
09/02/1999CA2321877A1 Method for cacheing configuration data of data flow processors and modules with a two- or multidimensional programmable cell structure (fpgas, dpgas or similar) according to a hierarchy
09/02/1999CA2321874A1 Method for configuring data flow processors and modules with a two- or multidimensional programmable cell structure (fpgas, dpgas or similar) without producing deadlocks
09/01/1999EP0939509A2 Wavelength division multiplexing optical transmission system
09/01/1999EP0939360A2 Switching mechanism and disk array apparatus having the switching mechanism
09/01/1999EP0939359A2 Dynamic ram disk
09/01/1999EP0939012A1 Method for verifying that information down-loaded to a computer is coherent
09/01/1999EP0938707A1 Arrangement for encryption/decryption of data and data carrier i ncorporating same
09/01/1999EP0938706A1 Data processor with localised memory reclamation
09/01/1999EP0938696A1 Method for ensuring security and control of access to data from a computer platform provided with a micro-computer
09/01/1999EP0536286B1 Distributed database security system
09/01/1999EP0512007B1 Cluster architecture for a highly parallel scalar/vector multiprocessor system
09/01/1999CN1227644A Method and apparatus for allowing distributed control of shared resources
09/01/1999CN1227387A Memory capacity switching method and semiconductor device to which the same applies
09/01/1999CN1227367A Memory protection method and device therefor
08/1999
08/31/1999USRE36286 Preemptive demount in an automated storage library
08/31/1999US5946718 For use in a processor
08/31/1999US5946717 Multi-processor system which provides for translation look-aside buffer address range invalidation and address translation concurrently
08/31/1999US5946716 Sectored virtual memory management system and translation look-aside buffer (TLB) for the same
08/31/1999US5946715 Page address space with varying page size and boundaries
08/31/1999US5946714 Semiconductor storage device utilizing address management tables and table state maps for managing data storage and retrieval
08/31/1999US5946713 Memory attribute palette
08/31/1999US5946711 System for locking data in a shared cache
08/31/1999US5946710 Selectable two-way, four-way double cache interleave scheme
08/31/1999US5946709 Shared intervention protocol for SMP bus using caches, snooping, tags and prioritizing
08/31/1999US5946708 Automated cache manager for storage devices
08/31/1999US5946705 Avoidance of cache synonyms
08/31/1999US5946703 Method for reading data in data reading and writing system
08/31/1999US5946699 Version management apparatus and method for data having link structure
08/31/1999US5946690 NDC consistency reconnect mechanism
08/31/1999US5946689 Distributed database system and method of detecting contention in data update involved in replication of database data
08/31/1999US5946685 In a computing system
08/31/1999US5946399 Fail-safe device driver and method
08/31/1999US5946262 RAM having multiple ports sharing common memory locations
08/31/1999US5946256 Semiconductor memory having data transfer between RAM array and SAM array
08/31/1999US5946246 Semiconductor memory device with built-in self test circuit
08/31/1999US5945998 Apparatus for displaying location and non-location information about the contents of files
08/31/1999US5945991 Method and apparatus for centering an image on a display monitor
08/31/1999US5944833 Integrated circuit and method for decorrelating an instruction sequence of a program
08/31/1999US5944828 Power supply controller in computer system for supplying backup power to volatile memory while the computer receives AC power
08/31/1999US5944823 Outside access to computer resources through a firewall
08/31/1999US5944819 Method and system to optimize software execution by a computer using hardware attributes of the computer
08/31/1999US5944815 Microprocessor configured to execute a prefetch instruction including an access count field defining an expected number of access
08/31/1999US5944796 System for transmitting data within a range such that the transmission data does not exceed prescribed units in response to transmission processing speed
08/31/1999US5944793 Computerized resource name resolution mechanism
08/31/1999US5944789 For serving clients in a data network
08/26/1999WO1999032994A3 Management in data structures
08/26/1999WO1999023784B1 Distributed web application server
08/26/1999DE19807872A1 Method of managing configuration data in data flow processors
08/25/1999EP0938091A2 Information recording system
08/25/1999EP0938052A2 Apparatus for accelerating navigation of hypertext pages using compound requests
08/25/1999EP0938047A1 Memory protection method and device therefor
08/25/1999EP0618535B1 EEPROM card with defective cell substitution and cache memory
08/25/1999EP0485110B1 Logical partitioning of a redundant array storage system
08/25/1999CN1226990A Programmable metallization cell and method of making
08/25/1999CN1226708A Forward progress on retried snoop hits
08/25/1999CN1226707A Cache coherency protocol including HR state
08/25/1999CN1226706A Cache coherency protocol having hovering (H) and recent (R) states
08/25/1999CN1226705A Cathe coherency protocol with independent implementation of optimized cathe operations
08/25/1999CN1226704A Cache coherency protocol for data processing system including multi-level memory hierarchy
08/25/1999CN1226700A Performance speculative misaligned load operations
08/24/1999US5943692 Mobile client computer system with flash memory management utilizing a virtual address map and variable length data
08/24/1999US5943691 Determination of array padding using collision vectors
08/24/1999US5943690 Data storage apparatus and method allocating sets of data
08/24/1999US5943687 Penalty-based cache storage and replacement techniques
08/24/1999US5943686 Multiple cache directories for non-arbitration concurrent accessing of a cache memory
08/24/1999US5943685 Method of shared intervention via a single data provider among shared caches for SMP bus
08/24/1999US5943684 Method and system of providing a cache-coherency protocol for maintaining cache coherency within a multiprocessor data-processing system
08/24/1999US5943683 Data processing method using record division storing scheme and apparatus therefor
08/24/1999US5943681 Semiconductor memory device having cache function
08/24/1999US5943675 Change log historian system for memory shared by multiple workstations
08/24/1999US5943650 Operation management system and operation management method
08/24/1999US5943623 Integrated control and signal processing in a cellular telephone
08/24/1999US5943501 Multiple processor, distributed memory computer with out-of-order processing
08/24/1999US5943482 Expansion card insertion and removal
08/24/1999US5943422 Steganographic techniques for securely delivering electronic digital rights management control information over insecure communication channels
08/24/1999US5943421 Processor having compression and encryption circuitry
08/24/1999US5943284 Semiconductor memory device
08/24/1999US5943283 Address scrambling in a semiconductor memory
08/24/1999US5943257 Ferroelectric memory device and data protection method thereof
08/24/1999US5943065 For generating graphics data
08/24/1999US5942004 Device and a method for storing data and corresponding error-correction information
08/24/1999US5941994 Technique for sharing hot spare drives among multiple subsystems
08/24/1999US5941991 Method of estimating power consumption of each instruction processed by a microprocessor
08/24/1999US5941979 Microprocessor architecture with a switch network and an arbitration unit for controlling access to memory ports
08/24/1999US5941974 Serial interface with register selection which uses clock counting, chip select pulsing, and no address bits
08/24/1999US5941962 Buffer management system for releasing a buffer area based on holding time and maximum allowable time when remaining buffer areas reached threshold
08/19/1999WO1999041675A1 Network image view server using efficient client-server, tiling and caching architecture
08/19/1999WO1999041671A1 Accessing a messaging unit from a secondary bus
08/19/1999WO1999041669A1 Method and apparatus for relaxing the fifo ordering constraint for memory accesses in a multi-processor asynchronous cache system
08/19/1999WO1999041668A1 Compression store free-space management
08/19/1999WO1999041664A1 Method and apparatus for transferring data from the cache of one node to the cache of another node
08/19/1999WO1999035802A8 System for delivering data content over a low bit rate transmission channel
08/19/1999WO1999018730A3 Multithread data processor
08/19/1999WO1999016015A3 Contactless proximity automated data collection system and method
08/19/1999DE19905541A1 Control of memory access in a machine with a memory with non uniform access
08/19/1999CA2327667A1 Network image view server using efficient client-server, tiling and caching architecture
08/18/1999EP0936558A2 Cache coherency protocol having hovering (H) and recent (R) states
08/18/1999EP0936557A2 Cache coherency protocol for a data processing system including a multilevel memory hierarchy
08/18/1999EP0936556A2 Cache coherency protocol including a hovering state (HR)
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