| Patents for G06F 12 - Accessing, addressing or allocating within memory systems or architectures (152,539) |
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| 09/15/1999 | CN1228857A Microprocessor, particularly for use in chip card with control unit and housing surrounding control unit |
| 09/15/1999 | CN1228855A Error recognition in storage system |
| 09/15/1999 | CN1228854A Persistent heap for dynamic picture objects |
| 09/15/1999 | CN1228853A Semiconductor circuit, particularly for use in integrated module |
| 09/15/1999 | CN1228558A Program transformation method and program transformation system |
| 09/14/1999 | US5953748 Processor with an efficient translation lookaside buffer which uses previous address computation results |
| 09/14/1999 | US5953747 Apparatus and method for serialized set prediction |
| 09/14/1999 | US5953746 Method and apparatus for dynamically resizing a frame buffer in a shared memory buffer architecture system |
| 09/14/1999 | US5953745 Redundant memory array |
| 09/14/1999 | US5953743 Computer-implemented method |
| 09/14/1999 | US5953741 Stack cache for stack-based processor and method thereof |
| 09/14/1999 | US5953740 Computer memory system having programmable operational characteristics based on characteristics of a central processor |
| 09/14/1999 | US5953739 Synchronous DRAM cache using write signal to determine single or burst write |
| 09/14/1999 | US5953738 DRAM with integral SRAM and arithmetic-logic units |
| 09/14/1999 | US5953737 Method and apparatus for performing erase operations transparent to a solid state storage system |
| 09/14/1999 | US5953736 Write barrier system and method including pointer-specific instruction variant replacement mechanism |
| 09/14/1999 | US5953732 Computer-implemented method |
| 09/14/1999 | US5953729 In a computer system |
| 09/14/1999 | US5953728 System for modifying a database using a transaction log |
| 09/14/1999 | US5953538 Method and apparatus providing DMA transfers between devices coupled to different host bus bridges |
| 09/14/1999 | US5953510 Bidirectional data bus reservation priority controls having token logic |
| 09/14/1999 | US5953419 Cryptographic file labeling system for supporting secured access by multiple users |
| 09/14/1999 | US5953416 Data processing apparatus |
| 09/14/1999 | US5953286 Semiconductor memory |
| 09/14/1999 | US5953268 Memory block replacement system and replacement method for a semiconductor memory |
| 09/14/1999 | US5953241 Multiplier array processing system with enhanced utilization at lower precision for group multiply and sum instruction |
| 09/14/1999 | US5951677 Efficient hardware implementation of euclidean array processing in reed-solomon decoding |
| 09/14/1999 | US5951657 Cacheable interface control registers for high speed data transfer |
| 09/14/1999 | US5951655 External storage subsystem having independent access paths for permitting independent access from a host and a storage device to respective cache memories |
| 09/14/1999 | CA2246948C Method and means for encoding storing and retrieving hierarchical data processing information for a computer system |
| 09/14/1999 | CA2246946C Method and means for encoding storing and retrieving hierarchical data processing information for a computer system |
| 09/10/1999 | WO1999045482A1 Method, apparatus, system, and program product for attaching files and other objects to a partially replicated database |
| 09/10/1999 | WO1999045481A1 Transparent garbage collection of resources |
| 09/10/1999 | WO1999045474A2 Speed-optimized cache system |
| 09/10/1999 | WO1999045472A1 Multi-processor system with shared memory |
| 09/10/1999 | WO1999045456A1 File access control in a multi-protocol file server |
| 09/10/1999 | WO1999019802A3 Space-limited marking structure for tracing garbage collectors |
| 09/09/1999 | DE19904049A1 Multiprocessor network system with controller to distinguish between memory access and coherence operations |
| 09/09/1999 | DE19809640A1 Geschwindigkeitsoptimiertes Cachesystem Speed optimized cache system |
| 09/08/1999 | EP0940945A2 A method and apparatus for certification and safe storage of electronic documents |
| 09/08/1999 | EP0940850A1 Signaling improvement using extended transmission lines on 'DIMM'memory modules |
| 09/08/1999 | EP0940755A1 Methods and apparatus for generational dynamic management of computer memory |
| 09/08/1999 | EP0940743A1 Compact transparent dongle device |
| 09/08/1999 | EP0940037A1 Detecting a watermark embedded in an information signal |
| 09/08/1999 | EP0939957A2 Programmable metallization cell structure and method of making same |
| 09/08/1999 | EP0939926A2 Method and security system for processing a security critical activity |
| 09/08/1999 | CN1228176A Data de-rotator and de-interleaver |
| 09/08/1999 | CN1227932A Cache memory system which assures normal operation in synchronous cache access and access method to cache memory |
| 09/07/1999 | US5950232 Fetching apparatus for fetching data from a main memory |
| 09/07/1999 | US5950231 Memory manager system |
| 09/07/1999 | US5950229 System for accelerating memory bandwidth |
| 09/07/1999 | US5950228 In a computer system |
| 09/07/1999 | US5950227 For a computer system |
| 09/07/1999 | US5950226 Multiprocessing system employing a three-hop communication protocol |
| 09/07/1999 | US5950222 Microcomputer using a non-volatile memory |
| 09/07/1999 | US5950221 In a computer system |
| 09/07/1999 | US5950220 Method and apparatus for providing a logical double sided memory element by mapping single sided memory elements onto a logical double sided memory address space |
| 09/07/1999 | US5950214 System, method, and computer program product for accessing a note database having subnote information for the purpose of manipulating subnotes linked to portions of documents |
| 09/07/1999 | US5950208 Hyper text system and its display method |
| 09/07/1999 | US5950205 Data transmission over the internet using a cache memory file system |
| 09/07/1999 | US5950203 Method and apparatus for high-speed access to and sharing of storage devices on a networked digital data processing system |
| 09/07/1999 | US5950013 Memory card with submemory |
| 09/07/1999 | US5950007 Method for compiling loops containing prefetch instructions that replaces one or more actual prefetches with one virtual prefetch prior to loop scheduling and unrolling |
| 09/07/1999 | US5949970 Dual XPCS for disaster recovery |
| 09/07/1999 | US5949876 Systems and methods for secure transaction management and electronic rights protection |
| 09/07/1999 | US5949736 Memory control circuit reducing a consumed power of memory |
| 09/07/1999 | US5949702 Memory mounting judgment circuit |
| 09/07/1999 | US5949436 Accelerated graphics port multiple entry gart cache allocation system and method |
| 09/07/1999 | US5949252 Bus configuration and input/output buffer |
| 09/07/1999 | US5948110 Method for providing parity in a raid sub-system using non-volatile memory |
| 09/07/1999 | US5948102 Method and device to improve the security of an integrated circuit |
| 09/07/1999 | US5948099 Apparatus and method for swapping the byte order of a data item to effectuate memory format conversion |
| 09/07/1999 | US5948097 Method and apparatus for changing privilege levels in a computer system without use of a call gate |
| 09/07/1999 | US5948082 Computer system having a data buffering system which includes a main ring buffer comprised of a plurality of sub-ring buffers connected in a ring |
| 09/07/1999 | US5948067 Converting between an internal cell and multiple standard asynchronous transfer mode cells |
| 09/07/1999 | US5948062 Network file server using a cached disk array storing a network file directory including file locking information and data mover computers each having file system software for shared read-write file access |
| 09/07/1999 | CA2145361C Buffer manager |
| 09/07/1999 | CA2130979C Protected programmable memory cartridge and computer system using same |
| 09/05/1999 | CA2263776A1 Compact transparent dongle device |
| 09/03/1999 | CA2262353A1 Network directory access mechanism |
| 09/02/1999 | WO1999044378A1 Sim-card with directory entries for mobile telephones |
| 09/02/1999 | WO1999044296A2 Apparatus and method for dynamically verifying information in a distributed system |
| 09/02/1999 | WO1999044202A1 Recording/reproducing device and recording/reproducing method |
| 09/02/1999 | WO1999044158A1 Method and system for typesafe attribute matching |
| 09/02/1999 | WO1999044157A1 Method and system for multi-entry and multi-template matching in a database |
| 09/02/1999 | WO1999044156A1 Method and system for in-place modifications in a database |
| 09/02/1999 | WO1999044147A2 METHOD FOR CACHEING CONFIGURATION DATA OF DATA FLOW PROCESSORS AND MODULES WITH A TWO- OR MULTIDIMENSIONAL PROGRAMMABLE CELL STRUCTURE (FPGAs, DPGAs OR SIMILAR) ACCORDING TO A HIERARCHY |
| 09/02/1999 | WO1999044138A2 Stack-based security requirements |
| 09/02/1999 | WO1999044137A2 Stack-based access control |
| 09/02/1999 | WO1999044133A2 Method and system for deterministic hashes to identify remote methods |
| 09/02/1999 | WO1999044130A1 Method, apparatus, and product for leasing of delegation certificates in a distributed system |
| 09/02/1999 | WO1999044129A1 Method, apparatus, and product for leasing of group membership in a distributed system |
| 09/02/1999 | WO1999044128A1 Leasing for failure detection |
| 09/02/1999 | WO1999044127A1 Dynamic lookup service in a distributed system |
| 09/02/1999 | WO1999044125A1 Method and system for leasing storage |
| 09/02/1999 | WO1999044120A2 METHOD FOR CONFIGURING DATA FLOW PROCESSORS AND MODULES WITH A TWO- OR MULTIDIMENSIONAL PROGRAMMABLE CELL STRUCTURE (FPGAs, DPGAs OR SIMILAR) WITHOUT PRODUCING DEADLOCKS |
| 09/02/1999 | WO1999044119A2 A method and apparatus for transporting behavior in an event-based distributed system |
| 09/02/1999 | WO1999044115A2 Per-method designation of security requirements |
| 09/02/1999 | WO1999044113A2 Increasing the memory performance of flash memory devices by writing sectors simultaneously to multiple flash memory devices |
| 09/02/1999 | DE19835244A1 Memory capacity switching method |