Patents for H03L 7 - Automatic control of frequency or phase; Synchronisation (37,643)
10/2002
10/01/2002US6459342 System and method for controlling an oscillator
10/01/2002US6459314 Delay locked loop circuit having duty cycle correction function and delay locking method
10/01/2002US6459313 IO power management: synchronously regulated output skew
10/01/2002US6459312 Semiconductor integrated circuit, delay-locked loop having the same circuit, self-synchronizing pipeline type system, voltage-controlled oscillator, and phase-locked loop
10/01/2002US6459310 Divide by 15 clock circuit
10/01/2002US6459309 Frequency converter enabling a non-integer division ratio to be programmed by means of a unique control word
10/01/2002US6459253 Bandwidth calibration for frequency locked loop
09/2002
09/26/2002WO2002076009A1 Fractional-n frequency synthesizer with fractional compensation method
09/26/2002WO2002075927A2 Frequency closed loop for frequency modulation
09/26/2002WO2002075497A2 Methods and apparatus for delivering multimedia communications services to multiple tenants in a building
09/26/2002WO2002060062A3 Phase-locked loop with conditioned charge pump output
09/26/2002WO2002021282A8 Method and apparatus for estimating physical parameters in a signal
09/26/2002US20020138540 Multiplier circuit
09/26/2002US20020136343 Analog unidirectional serial link architecture
09/26/2002US20020136342 Sample and hold type fractional-N frequency synthesezer
09/26/2002US20020136341 Fractional-N frequency synthesizer with fractional compensation method
09/26/2002US20020136340 Two-stage multiplier circuit
09/26/2002US20020136241 Digital visual interface with audio and auxiliary data
09/26/2002US20020135480 Automatic wireless synchronization of electronic article surveillance systems
09/26/2002US20020135428 Apparatus and method for phase lock loop gain control using unit current sources
09/26/2002US20020135417 Gm-C tuning circuit with filter configuration
09/26/2002US20020135409 Method for noise and power reduction for digital delay lines
09/26/2002US20020135403 Trigger circuit
09/26/2002US20020135400 Digital frequency comparator
09/26/2002DE10161054A1 Takt- und Daten-Wiederherstellschaltung und Taktsteuerverfahren Clock and data recovery circuit and clock control method
09/26/2002DE10160507A1 Generating clock in data processing system with multiple independent non-synchronies digital data channels by using respective delay-locked-loops
09/26/2002DE10107175A1 Frequency disparity detection method for synchronisation network evaluates variation in voltage-controlled oscillator setting value for detecting characteristic drift
09/26/2002DE10102725A1 Verfahren zum Betreiben einer PLL-Frequenzsyntheseschaltung Method for operating a PLL frequency synthesis circuit
09/26/2002CA2442721A1 Fractional-n frequency synthesizer with fractional compensation method
09/25/2002EP1244216A2 Oversampling clock recovery circuit applicable not only to high rate data but also to low rate data
09/25/2002EP1244215A1 Phase lock loop gain control using unit current sources
09/25/2002EP1243087A2 A multi-rate transponder system and chip set
09/25/2002EP1243074A1 Phase detector for a phase-locked loop
09/25/2002EP1243069A1 Apparatus for measuring intervals between signal edges
09/25/2002EP1242860A2 Encoded clocks to distribute multiple clock signals to multiple devices in a computer system
09/25/2002EP1032988A4 Apparatus for low power radio communications
09/25/2002EP0821846B1 An apparatus and method for using negative fm feedback in high quality oscillator devices
09/25/2002CN1371549A PLL noise smoothing using dual-modulus interleaving
09/25/2002CN1371180A Moving station capable of controlling frequency automatically
09/25/2002CN1371171A Phase mixer and multiple-phase generator with the phase mixer
09/24/2002US6456831 Amplitude change time activated phase locked controller in a selective call receiver
09/24/2002US6456679 Phase-coupled clock signal generator and character generator comprising such a phase-coupled clock signal generator
09/24/2002US6456676 Clock signal distribution and synchronization
09/24/2002US6456170 Comparator and voltage controlled oscillator circuit
09/24/2002US6456166 Semiconductor integrated circuit and phase locked loop circuit
09/24/2002US6456165 Phase error control for phase-locked loops
09/24/2002US6456164 Sigma delta fractional-N frequency divider with improved noise and spur performance
09/24/2002US6456132 Phase-locked loop circuit
09/24/2002US6456131 Charge mirror circuit
09/24/2002US6456130 Delay lock loop and update method with limited drift and improved power savings
09/24/2002US6456129 Internal clock signal generator
09/24/2002US6456128 Oversampling clock recovery circuit
09/24/2002US6456109 Jitter detecting circuit for detecting cycle-to-cycle jitter
09/24/2002US6456092 Network vector channel analyzer
09/19/2002WO2002073807A1 Reference clock generator
09/19/2002WO2002073806A2 Pll cycle slip compensation
09/19/2002WO2002073801A1 Filter trimming
09/19/2002WO2002073791A2 Pll cycle slip detection
09/19/2002WO2002073789A1 Automatic tuning of vco
09/19/2002WO2002019528A3 Data recovery using data eye tracking
09/19/2002WO2002013390A3 Phase locked loop with controlled switching of reference signals
09/19/2002WO2001015324A9 Charge pump phase locked loop circuit
09/19/2002US20020133732 Network interface with double data rate and delay locked loop
09/19/2002US20020132598 PLL frequency synthesizer
09/19/2002US20020132595 FM transmitter
09/19/2002US20020131541 Spread spectrum modulation technique for frequency synthesizers
09/19/2002US20020131539 Clock and data recovery method and apparatus
09/19/2002US20020131538 Method and apparatus for asynchronous clock retiming
09/19/2002US20020131456 Network interface using programmable delay and frequency doubler
09/19/2002US20020130725 Jitter clean-up circuit for communications applications
09/19/2002US20020130724 Full digital phase locked loop and circuitry for utilizing the same
09/19/2002US20020130704 Charge pump circuit
09/19/2002US20020130691 Method and apparatus for fast lock of delay lock loop
09/19/2002US20020130689 Frequency synthesizer
09/19/2002US20020130684 CMOS output amplifier independent of temperature, supply voltage and manufacturing quality of transistors
09/19/2002DE10108636A1 Abgleichverfahren und Abgleicheinrichtung für PLL-Schaltung zur Zwei-Punkt-Modulation Matching methods and matching means for PLL circuit for two-point modulation
09/19/2002DE10106941A1 Phasen- und Frequenznachlaufsynchronisationsschaltungen Phase and frequency tracking synchronization circuits
09/18/2002EP1241846A2 Phase-locked loop initialization via curve-fitting
09/18/2002EP1241844A2 Combining a clock signal and a data signal
09/18/2002EP1241791A2 PLL frequency synthesizer
09/18/2002EP1241790A2 Full digital phase locked loop and circuitry for utilizing the same
09/18/2002EP1241789A2 Network interface with double data rate and delay locked loop
09/18/2002EP0940004B1 Apparatus for tracking resonant frequency
09/18/2002EP0829135B1 Phase shifting circuit and method for providing a phase shift
09/18/2002CN1370351A Phase detector for phase-locked loop
09/18/2002CN1370347A Electronic circuit arrangement generating transmit frequency
09/17/2002US6453181 Method and apparatus for compensating for frequency drift in a low frequency sleep clock within a mobile station operating in a slotted paging mode
09/17/2002US6452986 Detector tolerant of frequency misalignment
09/17/2002US6452458 Voltage-controlled oscillator
09/17/2002US6452432 Signal processing circuits having a pair of delay locked loop (DLL) circuits for adjusting a duty-cycle of a periodic digital signal and methods of operating same
09/17/2002US6452431 Scheme for delay locked loop reset protection
09/17/2002US6452430 Phase-locked loop circuit
09/17/2002CA2298863C Improved decision directed phase locked loop (dd-pll) for use with short block codes in digital communication systems
09/17/2002CA2231891C Radio apparatus
09/16/2002CA2376971A1 Combining a clock signal and a data signal
09/12/2002WO2002071682A1 Method and apparatus for adjusting the clock delay in systems with multiple integrated circuits
09/12/2002WO2002071647A1 Delay lock loops for wireless communication systems
09/12/2002WO2002071614A1 Sigma delta fractional-n frequency divider with improved noise and spur performance
09/12/2002WO2002071613A1 Feedback loop with slew rate limiter
09/12/2002WO2002054648A3 Data de-skew method and system