Patents
Sitemap › H03 - Basic electronic circuitry › H03L - Automatic control, starting, synchronisation, or stabilisation of generators of electronic oscillations or pulses › H03L 7 - Automatic control of frequency or phase; Synchronisation
Patents for H03L 7 - Automatic control of frequency or phase; Synchronisation (37,643)
11/2007
11/15/2007US20070263122 Digital Image Transmission Apparatus
11/15/2007US20070262826 Clock with regulated duty cycle and frequency
11/15/2007US20070262825 Embedded structure circuit for VCO and regulator
11/15/2007US20070262822 Digitally controlled oscillator with jitter shaping capability
11/15/2007US20070262799 On-chip signal waveform measurement apparatus for measuring signal waveforms at detection points on IC chip
11/15/2007US20070262798 Delay-locked loop apparatus and delay-locked method
11/14/2007EP1855382A1 Circuit and method for phase/frequency detection
11/14/2007EP1684466B1 Power saving and handling broadcast as unicast traffic in a WLAN
11/14/2007EP1421704B1 Methods and apparatus for clock and power control in wireless systems
11/14/2007CN200976046Y Positioning communication integrated dobber
11/14/2007CN101073202A Oscillator circuit, used in particular for mobile radio communication
11/14/2007CN101072296A No title available
11/14/2007CN101072029A Multiple precision clock generating circuit on single chip and its realizing method
11/14/2007CN101072028A Programmeable pseudo-random multi-frequency signal chip
11/14/2007CN101071612A Binary phase-shift keying modulated jitter clock recovery circuit and its method
11/14/2007CN100349378C Network synchronization slave clock phase-locked loop capable of integrating
11/13/2007US7295824 Frequency multiplier pre-stage for fractional-N phase-locked loops
11/13/2007US7295821 Multiple base station automatic frequency control architecture in wireless communication system
11/13/2007US7295643 Method and a device for phase and frequency comparison
11/13/2007US7295248 External synchronous signal generating circuit and phase difference measuring circuit
11/13/2007US7295080 Semiconductor integrated circuit having a switch circuit that outputs reference clock until PLL locks
11/13/2007US7295078 High-speed, accurate trimming for electronically trimmed VCO
11/13/2007US7295076 Synchronously coupled oscillator
11/13/2007US7295053 Delay-locked loop circuits
11/13/2007US7295052 Regenerative power-on control circuit
11/13/2007US7295051 System and method for monitoring a power supply level
11/13/2007US7295050 Power-up reset circuit with reduced power consumption
11/13/2007US7295049 Method and circuit for rapid alignment of signals
11/08/2007WO2007127403A2 Clock with regulated duty cycle and frequency
11/08/2007WO2007126820A1 Phase recovery from forward clock
11/08/2007WO2007125754A1 Signal receiving device
11/08/2007WO2007124788A1 Apparatus for phase synchronisation according to the master/slave principle
11/08/2007WO2007106414A3 Hybrid pll combining fractional-n & integer-n modes of differing bandwidths
11/08/2007WO2007064648A3 Communications distribution system
11/08/2007US20070261014 System and method for design entry and synthesis in programmable logic devices
11/08/2007US20070258555 Slave Device with Synchronous Interface for Use in Synchronous Memory System
11/08/2007US20070258554 Slave Device with Calibration Signal Generator for Synchronous Memory System
11/08/2007US20070257735 High frequency divider with input-sensitivity compensation
11/08/2007US20070257718 Spectrum spreaders including tunable filters and related devices and methods
11/08/2007US20070257717 Semiconductor integrated circuit having data input apparatus and method of inputting data using the same
11/08/2007US20070257716 Dft Technique for Stressing Self-Timed Semiconductor Memories to Detect Delay Faults
11/08/2007US20070257715 System and method for abstract configuration
11/08/2007DE102006018236A1 Controllable power source for use in integrated circuit, comprises two supply terminals to build two supply potentials, where power source has replication of current paths in their uncontrolled condition
11/08/2007DE102004045513B4 Oszillatorschaltung und diese enthaltende integrierte Schaltung Oscillator circuit and this integrated circuit containing
11/08/2007DE102004041656B4 Phasenregelkreis und Verfahren zum Abgleichen eines Schleifenfilters Phase-locked loop and method for adjusting a loop filter
11/07/2007CN200973076Y Integral phaselock loop frequency synthesizer
11/07/2007CN200973075Y Frequency synthesizer in OFDM system
11/07/2007CN101069240A Timing extraction device, and information reproduction apparatus and DVD device using the same
11/07/2007CN101067635A Method and system for determinging digital signal duty cycle
11/07/2007CN100347965C Transceiver using a harmonic rejection mixer
11/06/2007US7292832 Timing and frequency control method and circuit for digital wireless telephone system terminals
11/06/2007US7292670 System and method for automatically correcting duty cycle distortion
11/06/2007US7292668 Data processor and data processing method
11/06/2007US7292662 Feed forward clock and data recovery unit
11/06/2007US7292488 Temperature dependent self-refresh module for a memory device
11/06/2007US7292119 Phase locked loop frequency synthesizer
11/06/2007US7292118 Modulator
11/06/2007US7292110 Self-test digital phase-locked loop and method thereof
11/06/2007US7292108 Voltage controlled oscillator for frequency synthesizer
11/06/2007US7292107 Modulation method and apparatus with adjustable divisors of the dividers in phase-locked loop
11/06/2007US7292106 Phase-locked loop with conditioned charge pump output
11/06/2007US7292080 Delay locked loop using a FIFO circuit to synchronize between blender and coarse delay control signals
11/06/2007US7292079 DLL-based programmable clock generator using a threshold-trigger delay element circuit and a circular edge combiner
11/06/2007US7292078 Phase locked loop integrated circuits having fast locking characteristics and methods of operating same
11/06/2007US7292077 Phase-lock loop and loop filter thereof
11/06/2007US7292076 Low voltage pull-down circuit
11/01/2007WO2007052247A3 Apparatus and methods for radar imaging based on injected push-push oscillators
11/01/2007US20070253493 Digital broadcasting receiving unit and digital broadcasting system
11/01/2007US20070252737 Apparatus Comprising a Sigma-Delta Modulator and Method of Generating a Quantized Signal-Delta Modulator
11/01/2007US20070252654 Frequency modulator
11/01/2007US20070252653 Oscillation Controlling Apparatus, Recording Medium Having Program Recorded Thereon, and Channel Selecting Apparatus
11/01/2007US20070252627 Self-timed fine tuning control
11/01/2007US20070252626 All-digital power-on reset device
10/2007
10/31/2007EP1849234A1 Oscillator based on thermal diffusion
10/31/2007EP1668778B1 Delay control loop
10/31/2007EP1559225B1 Mechanism and method for audio system synchronization
10/31/2007EP1277286B9 Personal communications device with gps receiver and comon clock source
10/31/2007EP0961499B1 Predictive coding method and decoding method for dynamic image
10/31/2007DE10331893B4 Verfahren zum Sparen von Leistung durch Reduzierung der Zeit des aktiven Empfangs im Standby-Betrieb Method for conserving power by reducing the period of active reception in standby mode
10/31/2007DE10331092B4 Anordnung zur Phasensynchronisation von mehreren zu einem Meßsystem zusammengefaßten elektronischen Meßgeräten Arrangement for phase synchronization of several combined into a measuring system electronic measuring instruments
10/31/2007DE10258406B4 Verfahren zur Detektion der Phasenlage eines Signals in Bezug auf ein Digitalsignal und Phasendetektoranordnung A method for detecting the phase position of a signal with respect to a digital signal and phase detector arrangement
10/31/2007DE102004057186B4 PLL-Schaltung mit einem spannungsgesteuerten Oszillator PLL circuit having a voltage controlled oscillator
10/31/2007DE102004002437B4 Verzögerungsregelkreis, integrierte Schaltung und Betriebsverfahren Delay locked loop, integrated circuit and method of operation
10/31/2007CN200969575Y Directly digital synthesized controllable frequency synthesizer
10/31/2007CN101065900A Jitter reduction circuit and frequency synthesizer
10/31/2007CN101064520A Digital broadcasting receiving unit and digital broadcasting system
10/31/2007CN101064511A Pll circuit, method of preventing interference of the pll circuit and optical-disk apparatus having the pll circuit
10/31/2007CN101064510A Low phase spurious frequency synthesis method
10/31/2007CN101064509A Full phase parameter millimeter wave frequency synthesis method and synthesizer
10/31/2007CN101064508A Digitally controlled oscillator with jitter shaping capability
10/31/2007CN101064507A Method and circuit for sampling data
10/31/2007CN100346576C Locking-status judging circuit for digital PLL circuit
10/31/2007CN100346574C 相位比较电路和cdr电路 The phase comparator circuit and cdr circuit
10/30/2007US7289542 Method for operating a PLL frequency synthesis circuit
10/30/2007US7289000 Clock scaling to optimize PLL clock generation accuracy
10/30/2007US7288999 Pre-distortion system for a synthesizer having modulation applied in the reference path
10/30/2007US7288998 Voltage controlled clock synthesizer
10/30/2007US7288997 Phase lock loop and the control method thereof
10/30/2007US7288976 Charge pump circuit and method thereof
10/30/2007US7288975 Method and apparatus for fail-safe and restartable system clock generation
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