Patents
Sitemap › H03 - Basic electronic circuitry › H03K - Pulse technique › H03K 19 - Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
Patents for H03K 19 - Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits (41,996)
12/2010
12/16/2010US20100315127 Semiconductor integrated circuit device
12/16/2010US20100315126 Dynamic circuit with slow mux input
12/16/2010US20100315125 Dynamic domino circuit and integrated circuit including the same
12/16/2010US20100315124 Low power receiver circuit
12/16/2010US20100315123 Non-majority mqca magnetic logic gates and arrays based on misaligned magnetic islands
12/16/2010US20100315122 Memory controller that controls termination in a memory device
12/16/2010US20100315119 Memory controller calibration
12/16/2010US20100315118 Circuits and methods for testing fpga routing switches
12/16/2010US20100315117 Method of Acquiring a Plurality of Logic Signals, with Confirmation of State Validity
12/15/2010CN201674483U IRIG_B code decoding interface circuit
12/15/2010CN1624805B Shift register of safety providing configuration bit
12/15/2010CN101919162A Layout method for soft-error hard electronics, and radiation hardened logic cell
12/15/2010CN101917184A Four-redundancy discrete signal integrated circuit
12/15/2010CN101917183A Aircraft front and back cabin control authority conversion circuit
12/15/2010CN101917162A FPGA (Field Programmable Gate Array)-based bonded phase frequency doubling method and device
12/15/2010CN101420224B Output buffer circuit
12/15/2010CN101399003B Display device, driving method of the same and electronic apparatus using the same
12/15/2010CN101320968B Self-adapting circuit and its processing method
12/15/2010CN101017656B Display device
12/14/2010US7853916 Methods of using one of a plurality of configuration bitstreams for an integrated circuit
12/14/2010US7853911 Method and apparatus for performing path-level skew optimization and analysis for a logic design
12/14/2010US7852781 Managing communications settings
12/14/2010US7852590 Solid state memory decommissioner
12/14/2010US7852309 Scan driver and organic light emitting display device having the same
12/14/2010US7852122 Transmission circuit for transmitting a differential signal having pulse time larger than a predetermined minimum pulse time and CMOS semiconductor device
12/14/2010US7852121 Domino logic circuit and pipelined domino logic circuit
12/14/2010US7852120 Bi-directional buffer for open-drain or open-collector bus
12/14/2010US7852118 High speed conditional back bias virtual ground restoration circuit
12/14/2010US7852117 Hierarchical interface for IC system
12/14/2010US7852116 IC output signal path with switch, bus holder, and buffer
12/14/2010US7852115 Method and apparatus for safe power up of programmable interconnect
12/14/2010US7852114 Nonvolatile nanotube programmable logic devices and a nonvolatile nanotube field programmable gate array using same
12/14/2010US7852113 Leakage control
12/14/2010US7852112 On-die system and method for controlling termination impedance of memory device data bus terminals
12/14/2010US7852110 Controlling the slew-rate of an output buffer
12/14/2010US7852109 Method and apparatus for supplying a clock to a device under test
12/14/2010US7852108 Single event upset resilient programmable interconnect
12/14/2010US7852107 Single event upset mitigation
12/14/2010US7852106 Method and apparatus for ballistic single flux quantum logic
12/09/2010WO2010140556A1 Level shifter circuit, scanning line driver and display device
12/09/2010WO2010140322A1 Semiconductor integrated circuit
12/09/2010WO2010140276A1 Input-output circuit
12/09/2010WO2010095819A3 Liquid crystal display driving circuit with less current consumption
12/09/2010US20100308866 Semiconductor buffer circuit
12/09/2010US20100308865 Semiconductor device
12/09/2010US20100308864 Flip-flop circuit having scan function
12/09/2010US20100308863 Architecture of Function Blocks and Wirings in a Structured ASIC and Configurable Driver Cell of a Logic Cell Zone
12/09/2010US20100308862 Element Controller for a Resilient Integrated Circuit Architecture
12/09/2010US20100308861 Termination circuit and impedance matching device including the same
12/09/2010US20100308860 Semiconductor device
12/09/2010US20100308859 Local Interconnect Network Transceiver Driver
12/09/2010US20100308858 Semiconductor device and semiconductor signal processing apparatus
12/09/2010DE102004013641B4 Schaltung mit Stromschaltlogik für die bidirektionale Datenübertragung Circuit current switching logic for bidirectional data transfer
12/08/2010EP2259433A1 Apparatus and method for processing parallel digital input signals from plurality of circuit breakers
12/08/2010EP2259431A1 PLD architecture for flexible placement of IP function blocks
12/08/2010EP2259430A1 Semiconductor integrated circuit and method of saving and recovering its internal state.
12/08/2010EP2259268A2 Semiconductor device
12/08/2010CN201667647U Resistive superconducting asynchronous double rail logic universal type door circuit
12/08/2010CN201667646U Long-time low-zero drift digital integrator based on field programmable gate array
12/08/2010CN1764069B Voltage level converter
12/08/2010CN1679237B Apparatus and mehtod for reducing power consumption in logical circuit, and the logical circuit
12/08/2010CN1667957B Highly configurable PLL architecture for programmable logic device, method and circuit products applying the same
12/08/2010CN1588819B Information transmission system and method and its output signal driving device
12/08/2010CN101911492A Charge recycling a 1-of-N NDL gate with a time varying power supply
12/08/2010CN101911491A Methods for analyzing scan chains, and for determining numbers or locations of hold time faults in scan chains
12/08/2010CN101911490A Output buffer circuit and output buffer system
12/08/2010CN101908881A Directional coupler and radio-frequency power amplifier containing same
12/08/2010CN101908880A 电平移位器 The level shifter
12/08/2010CN101908879A Buffering circuit
12/08/2010CN101908878A Time sequence improving circuit
12/08/2010CN101908877A Headswitch and footswitch circuitry for power management
12/08/2010CN101908381A Shift register
12/08/2010CN101907901A Band gap circuit
12/08/2010CN101907897A Temperature control circuit and protection device thereof
12/08/2010CN101577504B Semi-conductor integrated circuit device
12/08/2010CN101304252B Level translation circuit
12/08/2010CN101295204B Multiphase voltage regulator on motherboard
12/08/2010CN101136160B Images display systems and image display driving method
12/08/2010CN101095232B Input stage resistant against negative voltage swings
12/07/2010USRE41982 Circuitry to provide a low power input buffer
12/07/2010US7848457 Constant delay zero standby differential logic receiver and method
12/07/2010US7847596 Electrical device for performing logic functions
12/07/2010US7847595 Input circuit and semiconductor integrated circuit comprising the input circuit
12/07/2010US7847594 Data output circuit of a semiconductor integrated circuit
12/07/2010US7847593 Semiconductor device, display device, and electronic device
12/07/2010US7847592 Buffer circuit of semiconductor memory apparatus
12/07/2010US7847591 Low jitter CMOS to CML converter
12/07/2010US7847590 Level shifter including cascode sets
12/07/2010US7847589 Configuration data feeding device
12/07/2010US7847588 Nonvolatile nanotube programmable logic devices and a nonvolatile nanotube field programmable gate array using same
12/07/2010US7847587 Semiconductor integrated circuit
12/07/2010US7847586 Integrate circuit chip with magnetic devices
12/07/2010US7847585 Source follower with active inductance as a load
12/07/2010US7847582 Logic circuit including a plurality of master-slave flip-flop circuits
12/07/2010US7847581 Device for protecting an integrated circuit against a laser attack
12/07/2010CA2424572C Asynchronous pipeline with latch controllers
12/02/2010WO2010137088A1 Interface circuit
12/02/2010US20100303467 Optoelectronic Logic Gate
12/02/2010US20100301903 Building block for a secure cmos logic cell library
12/02/2010US20100301901 Universal two-input logic gate that is configurable and connectable in an integrated circuit by a single mask layer adjustment
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