| Patents for H03K 19 - Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits (41,996) |
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| 02/08/2011 | US7886251 System and method for building configurable designs with hardware description and verification languages |
| 02/08/2011 | US7886240 Modifying layout of IC based on function of interconnect and related circuit and design structure |
| 02/08/2011 | US7886130 Field programmable gate array and microcontroller system-on-a-chip |
| 02/08/2011 | US7885282 Dynamic control of physical layer quality on a serial bus |
| 02/08/2011 | US7884649 Selection of optimal clock gating elements |
| 02/08/2011 | US7884648 Pseudo-differential interfacing device having a switching circuit |
| 02/08/2011 | US7884647 Output driver |
| 02/08/2011 | US7884646 No stress level shifter |
| 02/08/2011 | US7884645 Voltage level shifting circuit and method |
| 02/08/2011 | US7884644 Techniques for adjusting level shifted signals |
| 02/08/2011 | US7884643 Low leakage voltage level shifting circuit |
| 02/08/2011 | US7884642 System LSI |
| 02/08/2011 | US7884641 Setting operating mode of an interface using multiple protocols |
| 02/08/2011 | US7884640 PLD providing soft wakeup logic |
| 02/08/2011 | US7884639 On-chip source termination in communication systems |
| 02/08/2011 | US7884635 Integrated circuit, system and method including a performance test mode |
| 02/03/2011 | WO2011014276A1 Enhanced immunity from electrostatic discharge |
| 02/03/2011 | WO2011013298A1 Sram cell |
| 02/03/2011 | WO2010129873A3 Drive supporting multiple signaling modes |
| 02/03/2011 | US20110026334 Bidirectional equalizer with cmos inductive bias circuit |
| 02/03/2011 | US20110025409 Semiconductor integrated circuit device |
| 02/03/2011 | US20110025378 Semiconductor integrated circuit and layout method thereof |
| 02/03/2011 | US20110025377 Circuit Arrangement and Method for Evaluating a Data Signal |
| 02/03/2011 | US20110025376 System for the flexible configuration of functional modules |
| 02/03/2011 | US20110025375 Cmos circuitry with mixed transistor parameters |
| 02/03/2011 | US20110025373 Semiconductor devices having ZQ calibration circuits and calibration methods thereof |
| 02/03/2011 | US20110025372 Method and apparatus for reducing radiation and cross-talk induced data errors |
| 02/02/2011 | EP2279560A1 Configurable ic with packet switch configuration network |
| 02/02/2011 | EP2011236B1 Electronic circuit |
| 02/02/2011 | CN101965684A Level shifting circuit and method |
| 02/02/2011 | CN101964654A System and method for high-order asymmetric correction |
| 02/01/2011 | US7882465 FPGA and method and system for configuring and debugging a FPGA |
| 02/01/2011 | US7880506 Resolving metastability |
| 02/01/2011 | US7880505 Low power reconfigurable circuits with delay compensation |
| 02/01/2011 | US7880504 Logic stages with inversion timing control |
| 02/01/2011 | US7880503 Method of driving gate lines, gate line drive circuit for performing the method and display device having the gate line drive circuit |
| 02/01/2011 | US7880502 Logic circuit |
| 02/01/2011 | US7880501 Integrated circuit devices having level shifting circuits therein |
| 02/01/2011 | US7880500 Logical signal voltage converter |
| 02/01/2011 | US7880499 Reconfigurable logic fabrics for integrated circuits and systems and methods for configuring reconfigurable logic fabrics |
| 02/01/2011 | US7880498 Adjustable hold flip flop and method for adjusting hold requirements |
| 02/01/2011 | US7880497 Fault tolerant integrated circuit architecture |
| 02/01/2011 | US7880496 Conservative logic gate for design of quantum dot cellular automata circuits |
| 02/01/2011 | US7880330 Controlling a power converter |
| 01/27/2011 | WO2011011639A2 Level shifters and high voltage logic circuits |
| 01/27/2011 | WO2011011638A2 High voltage logic circuits |
| 01/27/2011 | WO2011009905A1 Microwave switching structure having a distributed amplifier with an input for feeding a test signal therein |
| 01/27/2011 | WO2011009409A1 Jtag apparatus and method for implementing jtag data transmission |
| 01/27/2011 | WO2010111619A3 Voltage mode transmitter equalizer |
| 01/27/2011 | WO2009102456A3 Output driver with overvoltage protection |
| 01/27/2011 | US20110019787 Method and Apparatus Synchronizing Integrated Circuit Clocks |
| 01/27/2011 | US20110018584 Semiconductor integrated circuit |
| 01/27/2011 | US20110018583 High voltage logic circuits |
| 01/27/2011 | US20110018582 Configuration context switcher with a clocked storage element |
| 01/27/2011 | US20110018581 Multi-functional logic gate device and programmable integrated circuit device using the same |
| 01/26/2011 | EP2278790A2 Automatic equalization of video signals |
| 01/26/2011 | EP2278714A1 Power stage |
| 01/26/2011 | EP2278712A1 Integrated circuit including a broadband high-voltage buffer circuit |
| 01/26/2011 | EP2277267A2 Clock distribution buffer |
| 01/26/2011 | EP1378060B1 Monotonic dynamic-static pseudo-nmos logic circuit and method of forming a logic gate array |
| 01/26/2011 | CN201726386U Hyperchaos/chaos system universal analog circuit |
| 01/26/2011 | CN1780964B Wear assembly for excavator digging edge |
| 01/26/2011 | CN101960719A Nonvolatile storage gate and its operating method, and logic circuit incorporating nonvolatile storage gate and its operating method |
| 01/26/2011 | CN101958707A Sampling circuits |
| 01/26/2011 | CN101958706A PROFIBUS-PA (Process Field Bus-Process Automation) based process automation field instrument communication module |
| 01/26/2011 | CN101958705A Signal regulation system and signal regulation method |
| 01/26/2011 | CN101958701A outage delay circuit, method and sound system with outage delay |
| 01/26/2011 | CN101430573B Control circuit for a bandgap circuit |
| 01/26/2011 | CN101414446B Data transmission system and method thereof |
| 01/26/2011 | CN101404490B Current-mode differential transmitter and receiver |
| 01/26/2011 | CN101399532B Semiconductor elements |
| 01/26/2011 | CN101114435B Driver circuit and display apparatus |
| 01/25/2011 | US7877719 Fast dual-Vdd buffer insertion and buffered tree construction for power minimization |
| 01/25/2011 | US7877236 Trimming of operative parameters in electronic devices based on corrections mappings |
| 01/25/2011 | US7876630 Postamble timing for DDR memories |
| 01/25/2011 | US7876483 Optically reconfigurable logic circuit |
| 01/25/2011 | US7876142 Latch inverter and flip-flop using the same |
| 01/25/2011 | US7876131 Dual gate transistor keeper dynamic logic |
| 01/25/2011 | US7876130 Data transmitting device and data receiving device |
| 01/25/2011 | US7876129 Load sense and active noise reduction for I/O circuit |
| 01/25/2011 | US7876128 Voltage sequence output circuit |
| 01/25/2011 | US7876127 Automatic hold time fixing circuit unit |
| 01/25/2011 | US7876125 Register data retention systems and methods during reprogramming of programmable logic devices |
| 01/25/2011 | US7876124 Download sequencing techniques for circuit configuration data |
| 01/20/2011 | WO2011008356A2 Techniques for adjusting clock signals to compensate for noise |
| 01/20/2011 | WO2011007708A1 Measurement device and measurement method |
| 01/20/2011 | WO2011007642A1 Semiconductor device |
| 01/20/2011 | WO2010135097A3 Clock distribution techniques for channels |
| 01/20/2011 | US20110012642 Simultaneous lvds i/o signaling method and apparatus |
| 01/20/2011 | US20110012641 Cell arrangement method for designing semiconductor integrated circuit |
| 01/20/2011 | US20110012640 Configurable logic integrated circuit having a multidimensional structure of configurable elements |
| 01/20/2011 | US20110012639 Receiver, transceiver circuit, signal transmission method, and signal transmission system |
| 01/20/2011 | US20110012638 Methods and circuitry for reconfigurable seu/set tolerance |
| 01/20/2011 | DE102005009170B4 Logikschaltung und zugehöriges Verfahren Logic circuit and associated method |
| 01/19/2011 | EP2274830A1 High voltage tolerant input/output interface circuit |
| 01/19/2011 | CN1964193B Logical circuit |
| 01/19/2011 | CN101953075A A circuit for and method of minimizing power consumption in an integrated circuit device |
| 01/19/2011 | CN101951257A Dynamic logical gate circuit |
| 01/19/2011 | CN101951256A Single-phase clock pass transistor adiabatic logic circuit, full adder and 5-2 compressor |
| 01/19/2011 | CN101951255A Data processing circuit |