Patents for H01L 27 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate (229,248) |
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06/11/2002 | US6403494 Method of forming a floating gate self-aligned to STI on EEPROM |
06/11/2002 | US6403487 Method of forming separated spacer structures in mixed-mode integrated circuits |
06/11/2002 | US6403485 Method to form a low parasitic capacitance pseudo-SOI CMOS device |
06/11/2002 | US6403475 Fabrication method for semiconductor integrated device |
06/11/2002 | US6403472 Method of forming resistive contacts on intergrated circuits with mobility spoiling ions including high resistive contacts and low resistivity silicide contacts |
06/11/2002 | US6403455 Methods of fabricating a memory device |
06/11/2002 | US6403450 Heat treatment method for semiconductor substrates |
06/11/2002 | US6403444 Method for forming storage capacitor having undulated lower electrode for a semiconductor device |
06/11/2002 | US6403441 Method for fabricating storage capacitor using high dielectric constant material |
06/11/2002 | US6403439 Method of preparing for structural analysis a deep trench-type capacitor and method of structural analysis therefor |
06/11/2002 | US6403436 Semiconductor device and method of manufacturing the same |
06/11/2002 | US6403435 Method for fabricating a semiconductor device having recessed SOI structure |
06/11/2002 | US6403431 Method of forming in an insulating layer a trench that exceeds the photolithographic resolution limits |
06/11/2002 | US6403430 Semiconductor structure having more usable substrate area and method for forming same |
06/11/2002 | US6403429 Semiconductor processing methods of forming integrated circuitry, forming conductive lines, forming a conductive grid, forming a conductive network, forming an electrical interconnection to a node location, forming an electrical interconnection with a transistor source/drain region, and integrated circuitry |
06/11/2002 | US6403425 Dual gate oxide process with reduced thermal distribution of thin-gate channel implant profiles due to thick-gate oxide |
06/11/2002 | US6403424 Method for forming self-aligned mask read only memory by dual damascene trenches |
06/11/2002 | US6403422 Semiconductor device and method of manufacturing the same |
06/11/2002 | US6403421 Semiconductor nonvolatile memory device and method of producing the same |
06/11/2002 | US6403420 Nitrogen implant after bit-line formation for ONO flash memory devices |
06/11/2002 | US6403419 Method of manufacturing a flash memory device |
06/11/2002 | US6403413 Manufacturing method of semiconductor integrated circuit device having a capacitor |
06/11/2002 | US6403411 Method for manufacturing lower electrode of DRAM capacitor |
06/11/2002 | US6403409 Method for fabricating top gate type polycrystalline silicon thin film transistor |
06/11/2002 | US6403407 Method of forming fully self-aligned TFT with improved process window |
06/11/2002 | US6403406 Thin film transistor (tft); forming polycrystalline silicon and having an off-set area or a lightly doped drain (ldd) structure |
06/11/2002 | US6403404 Method of selectively forming a silicide layer on a logic area of a semiconductor substrate |
06/11/2002 | US6403403 Diode isolated thin film fuel cell array addressing method |
06/11/2002 | US6403396 Method for generation of electrically conducting or semiconducting structures in three dimensions and methods for erasure of the same structures |
06/11/2002 | US6403395 Electro-optical device, method for making the same, and electronic apparatus |
06/11/2002 | US6403394 Reduced leakage trench isolation |
06/11/2002 | US6403392 Method for patterning devices |
06/11/2002 | US6402974 Etching-back with controlled amounts of oxygen-containing feed gas using a plasma process; nonpitting |
06/06/2002 | WO2002045414A1 Image sensor output correcting device |
06/06/2002 | WO2002045233A1 Energy pathway arrangement |
06/06/2002 | WO2002045178A2 Protective cover and attachment method for moisture sensitive devices |
06/06/2002 | WO2002045176A1 Self-aligned non-volatile memory cell |
06/06/2002 | WO2002045175A1 Nonvolatile storage device and method for manufacturing nonvolatile storage device |
06/06/2002 | WO2002045174A1 Semiconductor device |
06/06/2002 | WO2002045171A1 Planar structure and methods of fabricating non-volatile memory devices |
06/06/2002 | WO2002045170A1 Flash-eeprom storage device and corresponding production method |
06/06/2002 | WO2002045169A1 Non-volatile nor single-transistor semiconductor memory cell |
06/06/2002 | WO2002045167A2 Thin films for magnetic devices |
06/06/2002 | WO2002045160A1 Flexible electronic device |
06/06/2002 | WO2002045158A2 Memory cell with vertical floating gate transistor |
06/06/2002 | WO2002045157A1 Simultaneous formation of charge storage and bitline to worldline isolation |
06/06/2002 | WO2002045156A2 Cmos fabrication process utilizing special transistor orientation |
06/06/2002 | WO2002045130A2 Embedded vertical dram cells and dual workfunction logic gates |
06/06/2002 | WO2002045090A2 Circuit for non-destructive, self-normalizing reading-out of mram memory cells |
06/06/2002 | WO2002044804A2 Pixellated devices such as active matrix liquid crystal displays |
06/06/2002 | WO2002028095A3 Imager with adjustable resolution |
06/06/2002 | WO2002025810A3 Mmic folded power amplifier |
06/06/2002 | WO2002025700A3 Semiconductor device and method of forming a semiconductor device |
06/06/2002 | WO2002018960A3 Device and method for characterizing the version of integrated circuits and use for controlling operations |
06/06/2002 | WO2002015276A3 Memory cell, memory cell device and method for the production thereof |
06/06/2002 | WO2002005268A3 All metal giant magnetoresistive memory |
06/06/2002 | WO2002003420A3 Integrated circuit radio architectures |
06/06/2002 | WO2002001568A3 Dynamic random access memory |
06/06/2002 | WO2001090882A3 Programmable single-chip device and related development environment |
06/06/2002 | WO2001088989A3 Unit cell with fan-out for large focal plane arrays with small detector pitch |
06/06/2002 | WO2001084553A3 Three-dimensional memory array and method of fabrication |
06/06/2002 | US20020069398 Correcting method of mask and mask manufactured by said method |
06/06/2002 | US20020069394 Method and circuits for performing offline circuit trimming |
06/06/2002 | US20020069392 Smart card and circuitry layout thereof |
06/06/2002 | US20020069374 Adjustable data delay using programmable clock shift |
06/06/2002 | US20020069041 Semiconductor device simulation apparatus as well as method and storage medium storing simulation program thereof |
06/06/2002 | US20020069027 Arrangement and method of testing an integrated circuit |
06/06/2002 | US20020068989 Method and apparatus for designing integrated circuits and storage medium for storing the method |
06/06/2002 | US20020068457 Method for forming silicon quantum dots and method for fabricating nonvolatile memory device using the same |
06/06/2002 | US20020068443 Semiconductor device and method of fabricating the same |
06/06/2002 | US20020068441 Top layers of metal for high performance IC's |
06/06/2002 | US20020068440 Methods of fabricating buried digit lines and semiconductor devices including same |
06/06/2002 | US20020068439 Method of manufacturing flash memory |
06/06/2002 | US20020068431 Encapsulated metal structures for semiconductor devices and MIM capacitors including the same |
06/06/2002 | US20020068428 Semiconductor device and method of manufacturing the same |
06/06/2002 | US20020068422 Heat treatment apparatus and method of manufacturing a semiconductor device |
06/06/2002 | US20020068420 Method for making an integrated circuit device with dielectrically isolated tubs and related circuit |
06/06/2002 | US20020068412 The electrodes are formed on an inner surface of the exposed lower capacitor electrode, reducing the likelihood of lower electrode breakage and shorting (e.g., stringer formation) during fabrication. electrode. |
06/06/2002 | US20020068405 Fabrication method for a semiconductor integrated circuit device |
06/06/2002 | US20020068403 Manufacturing method of a gate-split flash memory |
06/06/2002 | US20020068402 Nonvolatile semiconductor memory and process for fabricating the same |
06/06/2002 | US20020068398 Forms a spacer at the sidewall of a floating gate pattern to increase the surface area of the floating gate; increase a gate coupling ratio; reduce the distance between the floating gates to prohibit a seam phenomenon |
06/06/2002 | US20020068396 Silicon wafer with embedded optoelectronic material for monolithic OEIC |
06/06/2002 | US20020068395 Double LDD devices for improved DRAM refresh |
06/06/2002 | US20020068392 Method for fabricating thin film transistor including crystalline silicon active layer |
06/06/2002 | US20020068390 Method of forming semiconductor thin film and plastic substrate |
06/06/2002 | US20020068389 Fexible electronic device |
06/06/2002 | US20020068388 Semiconductor device and method of manufacturing the same |
06/06/2002 | US20020068387 Selective polysilicon stud growth |
06/06/2002 | US20020068380 Semiconductor device and manufacturing method thereof |
06/06/2002 | US20020068372 Thin-film semiconductor device |
06/06/2002 | US20020068192 First electrode disposed on a substrate, at least one organic luminescence function layer disposed on first electrode, second electrode, oxygen absorber; energy saving |
06/06/2002 | US20020068191 Organic electroluminescent device, method for manufacturing organic electroluminescent device, and electronic apparatus |
06/06/2002 | US20020067795 Apparatus and method of converting electromagnetic energy directly to electrons for computed tomography imaging |
06/06/2002 | US20020067651 Charge pump for negative differential resistance transistor |
06/06/2002 | US20020067642 Semiconductor memory |
06/06/2002 | US20020067641 Usage of word voltage assistance in twin MONOS cell during program and erase |
06/06/2002 | US20020067639 Row decoder of a NOR-type flash memory device |
06/06/2002 | US20020067637 Semiconductor memory |
06/06/2002 | US20020067636 Static semiconductor memory device |