Patents
Patents for H01L 27 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate (229,248)
07/2002
07/02/2002US6413825 Method for signal processing
07/02/2002US6413822 Super-self-aligned fabrication process of trench-gate DMOS with overlying device layer
07/02/2002US6413821 Method of fabricating semiconductor device including nonvolatile memory and peripheral circuit
07/02/2002US6413818 Method for forming a contoured floating gate cell
07/02/2002US6413816 Method for forming memory cell of semiconductor memory device
07/02/2002US6413814 Manufacture of a semiconductor device with retrograded wells
07/02/2002US6413812 Methods for forming ZPROM using spacers as an etching mask
07/02/2002US6413811 Method of forming a shared contact in a semiconductor device including MOSFETS
07/02/2002US6413810 Fabrication method of a dual-gate CMOSFET
07/02/2002US6413809 Method of manufacturing a non-volatile memory having an element isolation insulation film embedded in the trench
07/02/2002US6413808 Semiconductor device and process for production thereof
07/02/2002US6413806 Semiconductor device and method for protecting such device from a reversed drain voltage
07/02/2002US6413804 Method of fabrication of thin film transistor
07/02/2002US6413802 Finfet transistor structures having a double gate channel extending vertically from a substrate and methods of manufacture
07/02/2002US6413790 Preferred methods for producing electrical circuit elements used to control an electronic display
07/02/2002US6413788 Keepers for MRAM electrodes
07/02/2002US6413787 Method for fabricating dielectric film
06/2002
06/27/2002WO2002051217A2 Packaged integrated circuits and methods of producing thereof
06/27/2002WO2002050921A1 Optoelectronic component for conversion of electromagnetic radiation into an intensity-dependent photocurrent
06/27/2002WO2002050920A1 Quick response photocurrent multiplying device
06/27/2002WO2002050918A1 A complementary couple-carry field transistor and the system formed on a substrate
06/27/2002WO2002050914A2 A semiconductor device with bias contact
06/27/2002WO2002050913A2 Photovoltaic device forming a glazing
06/27/2002WO2002050912A1 Production method for soi wafer and soi wafer
06/27/2002WO2002050911A1 Ultra-low power basic blocks and their uses
06/27/2002WO2002050909A2 A switched electrostatic discharge ring for integrated circuits with multiple power inputs
06/27/2002WO2002050908A2 Gate length control for semiconductor chip design
06/27/2002WO2002050842A2 Method for reading out or in a status from or to a ferroelectrical transistor of a memory cell and memory matrix
06/27/2002WO2002049854A1 Integral organic light emitting diode printhead utilizing color filters
06/27/2002WO2002021157B1 Flat panel x-ray imager with gain layer
06/27/2002WO2002016955A3 Compound semiconductor hall sensor
06/27/2002WO2002015233A3 Integrated transistor devices
06/27/2002WO2002011199A3 Compensation circuit
06/27/2002WO2002009126A3 Spin valve structure
06/27/2002WO2001095376A3 Methods for forming rough ruthenium-containing layers and structures/methods using same
06/27/2002WO2001093323A3 Method of removing rie lag in a deep trench silicon etching step
06/27/2002WO2001071884A3 Integrated circuit having various operational modes
06/27/2002WO2001067490A3 Single tunnel gate oxidation process for fabricating nand flash memory
06/27/2002WO2001047117A9 High sheet mos resistor method and apparatus
06/27/2002US20020083407 Semiconductor integrated circuit device, circuit design apparatus, and circuit design method
06/27/2002US20020083405 Semiconductor device, semiconductor device design method, semiconductor device design method recording medium, and semiconductor device design support system
06/27/2002US20020083404 Semiconductor device, semiconductor device design method, semiconductor device design method recording medium, and semiconductor device design support system
06/27/2002US20020083402 Method and system for simulating integrated circuit designs
06/27/2002US20020083390 Three-dimensional memory array and method for storing data bits and ECC bits therein
06/27/2002US20020083389 Testing integrated circuits
06/27/2002US20020081851 Method of forming nonvolatile memory device utilizing a hard mask
06/27/2002US20020081841 Method of making a contact structure
06/27/2002US20020081836 Contact structure, semiconductor device and manufacturing method thereof
06/27/2002US20020081833 Patterning three dimensional structures
06/27/2002US20020081832 Intralevel decoupling capacitor, method of manufacture and testing circuit of the same
06/27/2002US20020081824 Implantation process using sub-stoichiometric, oxygen doses at different energies
06/27/2002US20020081822 Composite member and separating method therefor, bonded substrate stack and separating method therefor, transfer method for transfer layer, and SOI substrate manufacturing method
06/27/2002US20020081821 SOI/glass process for forming thin silicon micromachined structures
06/27/2002US20020081820 Lead zirconate titanate dielectric situated between elec-trodes; hardmasking with refractory nitride; removing portion of hardmask and ferroelectric material using chlorine, oxygen and fluorine bearing compounds
06/27/2002US20020081819 Electronic component with shielding and method for its production
06/27/2002US20020081814 Self-aligned double-sided vertical MIMcap
06/27/2002US20020081813 Prevents the resistance between its lower electrode and plug from increasing
06/27/2002US20020081812 Method of manufacturing semiconductor device
06/27/2002US20020081808 Structure and method for improved signal processing
06/27/2002US20020081807 Dual trench isolation for a phase-change memory cell and method of making same
06/27/2002US20020081806 NAND-type flash memory devices and methods of fabricating the same
06/27/2002US20020081805 Method and structure for an improved floating gate memory cell
06/27/2002US20020081804 Phase-change memory cell using silicon on insulator
06/27/2002US20020081803 Method of fabricating dram capacitor
06/27/2002US20020081802 Interconnect to plate contact/via arrangement for random access memory
06/27/2002US20020081799 Contact fabrication method for semiconductor device
06/27/2002US20020081796 Method for fabricating a non-volatile memory device
06/27/2002US20020081790 Process for producing a capacitor configuration
06/27/2002US20020081786 Process for direct integration of a thin-film silicon p-n junction diode with a magnetic tunnel junction
06/27/2002US20020081783 Uniform current distribution scr device for high voltage esd protection
06/27/2002US20020081766 Semiconductor device, production method thereof, and electronic device
06/27/2002US20020081761 Method of manufacturing a display unit of a flat display panel having a wide viewing angle
06/27/2002US20020081760 Individual detector performance in radiation detector arrays
06/27/2002US20020081753 Formation of arrays of microelectronic elements
06/27/2002US20020081752 Method for fabricating a capacitor in a semiconductor device
06/27/2002US20020081716 Semiconductor element and device for detecting organic molecules and method for measuring organic molecules using same
06/27/2002US20020081503 Method and apparatus for producing color filter, method and apparatus for manufacturing liquid crystal device, method and apparatus for manufacturing EL device, method of discharging material, apparatus for controlling head and electronic apparatus
06/27/2002US20020081502 Method of manufacturing photomask and method of manufacturing semiconductor integrated circuit device
06/27/2002US20020080669 Semiconductor integrated circuit device
06/27/2002US20020080668 Current controlled multi-state parallel test for semiconductor device
06/27/2002US20020080659 Highly integrated non-volatile memory cell array having a high program speed
06/27/2002US20020080656 Method of using an integrated circuit
06/27/2002US20020080647 Metal structure for a phase-change memory device
06/27/2002US20020080646 Thin film magnetic memory device including memory cells having a magnetic tunnel junction
06/27/2002US20020080645 Passivated magneto-resistive bit structure and passivation method therefor
06/27/2002US20020080644 Magnetic random access memory
06/27/2002US20020080643 Magnetic random access memory
06/27/2002US20020080641 Semiconductor memory device
06/27/2002US20020080640 Dynamic RAM-and semiconductor device
06/27/2002US20020080639 256 Meg dynamic random access memory
06/27/2002US20020080637 Triodic rectifier switch
06/27/2002US20020080537 Switched electrostatic discharge ring for integrated circuits with multiple power inputs
06/27/2002US20020080536 Electrostatic discharge protection device and method therefor
06/27/2002US20020080295 TFT active matrix liquid crystal display devices
06/27/2002US20020080266 Method of manufacture of a solid state image pickup device, and a flexible printed wiring board
06/27/2002US20020080265 Hermetically sealed digital detector
06/27/2002US20020080244 Host interface for imaging arrays
06/27/2002US20020080109 Active matrix substrate, display device and method for driving the display device
06/27/2002US20020080104 Semiconductor device
06/27/2002US20020079958 Signal processing semiconductor integrated circuit device